CY7C1347F-133AI Cypress Semiconductor Corp, CY7C1347F-133AI Datasheet - Page 4

• Manufacturer Part Number: CY7C1347F-133AI
• Description: SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347F-133AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4.5 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 1
• Number Of Words: 128K

Document #: 38-05213 Rev. *D
Pin Definitions
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQ
DQ
DQP
DQP
V
V
V
V
MODE
NC
(BGA,FBGA)
0,
DD
SS
DDQ
SSQ
A
1
2
3
A,
C,
A,
C,
Name
1,
A,
C,
BW
BW
DQ
DQ
A
DQP
DQP
B,
B
D
D
B,
D
A
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs
DQPs
V
V
V
V
MODE
NC
(100TQFP)
Name
[16:0]
DD
SS
DDQ
SSQ
1
2
3
[A:D]
Asynchronous
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
I/O Ground
I/O Power
Ground
Supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
I/O-
I/O
Address Inputs used to select one of the 128K address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
are sampled active. A
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, addresses presented to the device are captured in the address
registers. A
both asserted, only ADSP is recognized. ASDP is ignored when CE
HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, addresses presented to the device are captured in the address
registers. A
both asserted, only ADSP is recognized.
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has
to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are
placed in a three-state condition.
Ground for the core of the device.
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to V
should remain static during device operation. Mode Pin has an internal pull-up.
No Connects.
DDQ
[A:D]
or left floating selects interleaved burst sequence. This is a strap pin and
[1:0]
[1:0]
and BWE).
are also loaded into the burst counter. When ADSP and ADSC are
are also loaded into the burst counter. When ADSP and ADSC are
2
1
1
and CE
and CE
and CE
[1:0]
feeds the 2-bit counter.
3
2
3
to select/deselect the device. ADSP is ignored if CE
to select/deselect the device.
to select/deselect the device.
Description
CY7C1347F
1
1
, CE
is deasserted
Page 4 of 19
2
, and CE
3
1