CY7C1347F-133AI Cypress Semiconductor Corp, CY7C1347F-133AI Datasheet - Page 13

• Manufacturer Part Number: CY7C1347F-133AI
• Description: SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347F-133AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4.5 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 1
• Number Of Words: 128K

Document #: 38-05213 Rev. *D
Switching Waveforms
Read/Write Cycle Timing
Note:
19. The data bus (Q)remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
20. GW is HIGH
Data Out (Q)
Data In (D)
ADDRESS
BW[A:D]
ADSP
ADSC
BWE,
ADV
CLK
OE
CE
A1
High-Z
High-Z
t ADS
t CES
t AS
A2
t ADH
t CEH
t CH
t AH
Back-to-Back READs
t CYC
t CLZ
[17, 19, 20]
Q(A1)
t CL
(continued)
t CO
Q(A2)
t OEHZ
t WES
t DS
D(A3)
Single WRITE
A3
t DH
t WEH
DON’T CARE
A4
t OELZ
UNDEFINED
Q(A4)
BURST READ
Q(A4+1)
Q(A4+2)
Q(A4+3)
CY7C1347F
D(A5)
A5
Page 13 of 19
Back-to-Back
WRITEs
D(A6)
A6