CY7C1347F-133AI Cypress Semiconductor Corp, CY7C1347F-133AI Datasheet - Page 7

• Manufacturer Part Number: CY7C1347F-133AI
• Description: SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347F-133AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4.5 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 1
• Number Of Words: 128K

Document #: 38-05213 Rev. *D
Truth Table
Partial Truth Table for Read/write
WRITE Cycle, Suspend Burst Current
WRITE Cycle, Suspend Burst Current
Read
Read
Write Byte A – DQ
Write Byte B – DQ
Write Bytes B, A
Write Byte C– DQ
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D– DQ
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
Notes:
7. Table only lists a partial listing of the byte write combinations. Any combination of BW
Next Cycle
[2, 3, 4, 5, 6]
C
D
B
Function
A
Used
Add.
CE
[2, 7]
H
X
1
CE
X
X
2
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
CE
X
X
3
ZZ
L
L
BWE
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
[A:D]
ADSP ADSC ADV WRITE
is valid. Appropriate write will be done based on which byte write is active.
H
X
BW
H
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
L
L
D
H
H
BW
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
C
OE
X
X
BW
CY7C1347F
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
CLK
L-H
L-H
B
Page 7 of 19
BW
DQ
D
D
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
X
L
L
A