ISL5217KI Intersil, ISL5217KI Datasheet - Page 19

• Manufacturer Part Number: ISL5217KI
• Description: Up/Down Conv Mixer 2.5V 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5217KI

• Package: 196BGA
• Maximum Power Dissipation: 1970 mW
• Operating Supply Voltage: 2.5 V

Read Access to the Coefficient RAM
Channel Status
The present status of the channel is latched by the single
channel µP interface into the Status 0x16 register bits 11:0.
These bits represent the channel flushed, FIR and FIFO
overflow/underflow, FIFO read address, and FIFO almost and
empty flags. 0x16 bits 10:7 and bit 3 are or’ed and latched into
the Device Top Control 0x7e. The bits in 0x7e represent the
fault status of each channel and the saturation status of each
summer. The detection of a FIFO overflow puts the channel in
the off-line mode, unless disabled by assertion of 0x0c, bit 1.
The off-line function takes the channel off-line by forcing the
FIFO read address to ‘000’, which forces 0 data out of the FIFO.
The channel flushed status bit in control word 0x16, may be
monitored to find out when the zeroes have propagated through
the entire channel pipeline chain. The channel flushed status is
asserted 24 sample clocks after entering the off-line mode.
Once a channel fault is latched into the Top control 0x7e, 15:12
a write to this location is required to clear the faulted status.
Reset
There are two types of resets, a hard reset and a soft reset.
A hard reset can occur by asserting the input pin RESET, or
3. Load the RAM data to location 0x14 with the
4. Load the RAM data to location 0x14 with the
5. Load the RAM write address to location 0x15. A write
6. Wait 4 clock cycles before performing the next write to the
7. Repeat steps 2-6.
8. Return RAM control back to the channel by disabling the
1. Enable the µP hold mode by setting bit 12 of the Main
2. Load the RAM read address and 0x8X00 to location 0x15.
3. Wait 4 clock cycles between all of the above writes before
4. Repeat steps 2-3.
5. Return RAM control back to the channel by disabling the
qCoef<19:4>.
iCoef<19:4>.
strobe transfers the contents of the three previously
loaded registers at location 0x14 into the RAM location
specified by the contents of the register at location 0x15.
(Indirect address[15] =0, Indirect address[9:8] =’01’).
RAM data register.
µP hold mode.
Control register 0x0c and bit 12 of the Test Control
register 0x17.
Three read strobes are required to transfers the contents
of the RAM location specified by the contents of the
register at location 0x15 onto the read bus. Indirect
address[15] =1, Indirect address[9:8] =’01’, reads back the
iCoef value, Indirect address[15] =1, Indirect address[9:8]
=’10’, reads back the qCoef value, Indirect address[15] =1,
Indirect address[9:8] =’11’, reads back the iCoef<3:0>,
iShift<3:0>, qCoef<3:0>, qShift<3:0> value.
performing the next write to the Ram address register.
µP hold mode.
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ISL5217
by the µP issuing a reset command to the top control register
0x7F, bit 1. A hard reset affects the entire device, leaving the
QPUC in an idle state awaiting configuration. This type of
reset returns the master and slave registers to their default
values, clears the FIFO pointer, the NCO accumulators, the
RAM pointers, and zeroes the data RAM. The data RAM
locations are written with a zero value immediately after the
reset is deasserted.
A soft reset occurs by the µP issuing a reset command to the
channel’s immediate action control register 0xF, bit 1. A soft
reset is similar to the hard reset but does not clear the
master registers and its action is limited only to that channel.
A soft reset leaves the channel in an idle state, awaiting an
update to begin processing.
Update Control
There are several mechanisms for updating slave registers
from the master registers. If hardware UPDX and TXENX will
be used the following control bits should be programmed:
The 6 update mechanisms that are described below cause
the slave registers to be updated from the contents of the
corresponding master register.
1. Main control register 0x0c bit 5 must be set to 1 to enable
2. Serial control register 0x11 bits 7:6 should be
3. Serial control register 0x11 bits 5:4 should be
4. Update Mask control register 0x0e bits 10:1 should be set
1. Immediate Update - Set bit 15 of cword 0x0c to a 1 to
2. Hardware Update - If the channel hardware update is
3. Software Update - Upon assertion of a channel software
4. External Hardware TXENX Assertion - If the channel
5. Internal Hardware TXENX Assertion - If the internal
hardware TXENX and UPDX.
programmed to configure which TXENX a channel will
respond to.
programmed to configure which UPDX a channel will
respond to.
to configure which slave registers will be updated from
their corresponding master registers upon a non-
immediate channel update. Those registers with their
update mask bit set to 1 are enabled registers.
implement this mode. In immediate update mode, the
slave register is updated 4 CLKS after the master register
is written (update mask register is ignored).
enabled, upon assertion of UPDX, the enabled slave
registers are updated.
update (bit 0 of control register 0x0f), the enabled slave
registers are updated.
hardware txEnable is enabled, upon assertion of TXENX,
the enabled slave registers are updated.
hardware txEnable function is enabled (bit 5 of cword
0x0c), upon assertion of the internal TXENX (kicked off
by either type of dynamic channel update as described in
items 3 and 4 above), the enabled slave registers are
updated.
July 8, 2005
FN6004.3