ISL5217KI Intersil, ISL5217KI Datasheet - Page 36

• Manufacturer Part Number: ISL5217KI
• Description: Up/Down Conv Mixer 2.5V 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5217KI

• Package: 196BGA
• Maximum Power Dissipation: 1970 mW
• Operating Supply Voltage: 2.5 V

NOTES:
Coefficients RAM Read/Write Procedure (16-bit 2’s complement format)
Write access to the Coefficient RAMs when I not equal Q:
Read access to the I Coefficient RAM:
Read access to the Q Coefficient RAM:
Coefficients RAM Read/Write Procedure (24-bit floating point format)
Write access to the Coefficient RAMs:
Read access to the Coefficient RAM:
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM data to location 0x14 with the Q coefficient
3. Load the RAM data to location 0x14 with the I coefficient
4. Load the RAM write address to location 0x15. A write strobe transfers the contents of the register at location 0x14 into the RAM location
5. Wait 4 clock cycles before performing the next write to the RAM data register.
6. Repeat steps 2-5.
7. Return RAM control back to the channel by disabling the µP hold mode.
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM read address to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents of the register
3. Wait 4 clock cycles before performing the next write to the RAM address register.
4. Repeat steps 2-3.
5. Return RAM control back to the channel by disabling the µP hold mode.
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM read address to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents of the register
3. Wait 4 clock cycles before performing the next write to the RAM address register.
4. After all data has been loaded, return RAM control back to the channel by disabling the µP hold mode
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM data to location 0x14 with the iCoef<3:0>, iShift<3:0>, qCoef<3:0>, qShift<3:0>.
3. Load the RAM data to location 0x14 with the qCoef<19:4>.
4. Load the RAM data to location 0x14 with the iCoef<19:4>.
5. Load the RAM write address to location 0x15. A write strobe transfers the contents of the three previously loaded registers at location 0x14
6. Wait 4 clock cycles before performing the next write to the RAM data register.
7. Repeat steps 2-6.
8. Return RAM control back to the channel by disabling the µP hold mode.
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM read address to location 0x15. Three read strobes are required to transfers the contents of the RAM location specified by the
3. Wait 4 clock cycles between all of the above writes before performing the next write to the Ram address register.
4. Repeat steps 2-3.
5. Return RAM control back to the channel by disabling the µP hold mode.
15:0
BIT
specified by the contents of the register at location 0x15. (Indirect address[15] =0, Indirect address[9:8]=”01”).
at location 0x15 onto the read bus. (Indirect address[15] =1, Indirect address[9:8]=”01”).
at location 0x15 onto the read bus. (Indirect address[15] =1, Indirect address[9:8] =’10’).
into the RAM location specified by the contents of the register at location 0x15. (Indirect address[15] =0, Indirect address[9:8] =’01’).
contents of the register at location 0x15 onto the read bus. Indirect address[15] =1, Indirect address[9:8] =’01’, reads back the iCoef value,
Indirect address[15] =1, Indirect address[9:8] =’10’, reads back the qCoef value, Indirect address[15] =1, Indirect address[9:8] =’11’, reads
back the iCoef<3:0>, iShift<3:0>, qCoef<3:0>, qShift<3:0> value.
Filter coefficient
FUNCTION
TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x100-0x1ff (PAGE 1)
36
256 location RAM. Use this page when the I and Q coefficients are different.
TABLE 41. I AND Q CHANNEL COEFFICIENTS (15:0)
ISL5217
DESCRIPTION
July 8, 2005
FN6004.3