ISL5217KI Intersil, ISL5217KI Datasheet - Page 37

• Manufacturer Part Number: ISL5217KI
• Description: Up/Down Conv Mixer 2.5V 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5217KI

• Package: 196BGA
• Maximum Power Dissipation: 1970 mW
• Operating Supply Voltage: 2.5 V

NOTES:
Coefficients RAM Read/Write Procedure (2’s complement format only)
Write access to the Coefficient RAMs when I equal Q:
Read access to the Q Coefficient RAM:
NOTES:
FSRMode affects what is output on the channel FSRX pin, but only if TXENX control, control word 0x0c, bit 11 is set to one. The FSRMode<1:0> is
defined as:
To start the TXENX cycle function following a reset, the user must provide a normal channel update via one of the 2 possible update mechanisms
(software or hardware). An update also resets all of the TXENX counters and starts the device up in cycle 0 with TXENX high.
Write access to the TXENX cycle controls:
Read access to the TXENX cycle controls:
ADDRESS
INDIRECT
0x404 -
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM data to location 0x14 with the coefficient.
3. Load the RAM write address to location 0x15. A write strobe transfers the contents of the register at location 0x14 into the RAM location
4. Wait 4 clock cycles before performing the next write to the RAM data register.
5. Repeat steps 2-4.
6. Return RAM control back to the channel by disabling the µP hold mode.
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM read address to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents of the register
3. Wait 4 clock cycles before performing the next write to the RAM address register.
4. After all data has been loaded, return RAM control back to the channel by disabling the µP hold mode.
00 No change to FSRX output.
01 No change to FSRX output.
10 FSR = internal channel UPDX.
11 FSR = internal channel TXENX. TXENX SIB control (0x0c, bit 3) must be set when FSRMode 11 is utilized, otherwise a TXENX glitch will be
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the data to location 0x14.
3. Load the indirect write address to location 0x15. A write strobe transfers the contents of the register at location 0x14 into the location specified
4. Assert the write strobe again to update the configuration register.
5. Wait 4 clock cycles before performing the next write to the data register.
6. Repeat steps 2-5.
7. Return control back to the channel by disabling the µP hold mode.
Care should be utilized to only read registers back immediately after writing since loading indirect addr 0x15 with 040X causes 0x040X to get
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the read address to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents of the register at
3. Wait 4 clock cycles before performing the next write to the address register.
4. Return control back to the channel by disabling the µP hold mode.
0x400
0x401
0x402
0x403
0x406
0x407
15:0
BIT
specified by the contents of the register at location 0x15. (Indirect address[15] =0, Indirect address[9:8]=”11”).
at location 0x15 onto the read bus. (Indirect address[15] =1, Indirect address[9:8]=”11”).
observed on the rising edge of TXENX.
by the contents of the register at location 0x15. (Indirect address[15] =0).
loaded with indirect register 0x14’s contents.
location 0x15 onto the read bus. (Indirect address[15] =1).
Filter coefficient
TXENX Cycle 0 Low
TXENX Cycle 0 High
TXENX Cycle 1 Low
TXENX Cycle 1 High
Reserved
TXENX Cycle Lengths
FUNCTION
FUNCTION
TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x400-0x407 (PAGE 4)
TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x300-0x3ff (PAGE 3)
37
Not Used.
256 location RAM. Use this page when the I and Q coefficients are the same.
TXENX cycle 0 low time count <15:0>.
TXENX cycle 0 high time count <15:0>.
TXENX cycle 1 low time count <15:0>.
TXENX cycle 1 high time count <15:0>.
FSRMode<1:0>, cycle 1 length<4:0>, cycle 0 length<4:0>
TABLE 42. I AND Q CHANNEL COEFFICIENTS (15:0)
TABLE 43. TXENX CONTROL
ISL5217
DESCRIPTION
DESCRIPTION
July 8, 2005
FN6004.3