MACH211-15VC Lattice, MACH211-15VC Datasheet - Page 35

• Manufacturer Part Number: MACH211-15VC
• Description: CPLD MACH 2 Family 2.5K Gates 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: Lattice

Specifications of MACH211-15VC

• Package: 44TQFP
• Family Name: MACH 2
• Device System Gates: 2500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: 0 to 70 °C

44- PIN PLCC CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
I/O
V
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
CC
Block A
= Input
= Input/Output
= Supply Voltage
(CLK 0/I0) CLK0/I1
(TCK) CLK1/I2
(TDI) I0
I/O10
I/O11
GND
I/O5
I/O6
I/O7
I/O8
I/O9
7
8
9
10
11
15
16
12
13
14
17
18
6
19 20 21 22
5 4
MACH 1 & 2 Families
44-Pin PLCC
3 2
23 24 25 26
1 44 43 42
TDI
TCK
TMS
TDO = Test Data Out
= Test Data In
= Test Mode Select
= Test Clock
27 28
41 40
39
38
37
36
35
34
33
32
31
30
29
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O22
I/O21
14051K-018
Block B
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