MACH211-15VC Lattice, MACH211-15VC Datasheet - Page 46

• Manufacturer Part Number: MACH211-15VC
• Description: CPLD MACH 2 Family 2.5K Gates 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: Lattice

Specifications of MACH211-15VC

• Package: 44TQFP
• Family Name: MACH 2
• Device System Gates: 2500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: 0 to 70 °C

100-PIN TQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)
Top View
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
I/O
V
46
CC
I0/CLK0
I1/CLK1
= Input
= Input/Output
= Supply Voltage
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
GND
TCK
I/O8
I/O9
V
TDI
NC
CC
I5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Block D
Block A
MACH 1 & 2 Families
100-Pin TQFP
TDI
TCK
TMS
TDO = Test Data Out
= Test Data In
= Test Clock
= Test Mode Select
Block E
Block H
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
TDO
NC
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
V
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
14051K-029
CC