CS5396-KS Cirrus Logic Inc, CS5396-KS Datasheet - Page 14

• Manufacturer Part Number: CS5396-KS
• Description: ADC Dual Delta-Sigma 96KSPS 24-Bit Serial 28-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5396-KS

• Package: 28SOIC
• Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial (SPI)
• Input Type: Voltage
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar

A calibration of the tri-level delta-sigma modulator
should always be initiated following power-up and
after allowing sufficient time for the voltage on the
external VREF capacitor to settle. This is required
to minimize noise and distortion. It is also advised
that the CS5396/97 be calibrated after the device
has reached thermal equilibrium, approximately 10
seconds, to maximize performance.
Synchronization of Multiple Devices -
Stand Alone Mode
In systems where multiple ADCs are required, care
must be taken to achieve simultaneous sampling. It
is recommended that the rising edge of the CAL
signal be timed with a falling edge of MCLK to en-
sure that all devices will initiate a calibration and
synchronization sequence on the same rising edge
of MCLK. The absence of re-timing of the CAL
signal can result in a sampling difference of one
MCLK period.
SDATA
14
SDATA
LRCK
SCLK
LRCK
SCLK
23 22
23 22
9
9
8
8
Figure 2. Serial Data Format 0, Stand-Alone Mode, DFS low. Left Justified.
7
7
Figure 3. Serial Data Format 1, Stand-Alone Mode, DFS High. I
6
6
5
5
4
4
Left
3
3
MASTER
24-Bit Left Justified Data
Data Valid on Rising Edge of 64x SCLK
MCLK equal to 256x Fs
Left
MASTER
I S 24-Bit Data
Data Valid on Rising Edge of 64x SCLK
MCLK equal to 256x Fs
2
2
2
1
1
0
0
23 22
CONTROL PORT MODE
Access to Control Port Mode
The mode selection between Stand-Alone and Con-
trol Port Mode is determined by the state of the
SDATA1 pin 250 MCLK cycles following the in-
ternal power-on reset. A 47 k pull-up resistor on
SDATA1 will select the Control Port Mode. How-
ever, the control port will not respond to CCLK and
CDIN until the pull-up on the SDATA1 pin is re-
leased.
Internal Power-On Reset
The timing required to determine Control port
mode and I
power-on reset. The internal power-on reset re-
quires the power supply to exceed a threshold volt-
age. However, there is no external indication of
when the internal reset is activated. If precise tim-
ing of the Control port and I
quired, MCLK should not be applied until the
power supply has stabilized.
SLAVE
24-Bit Left Justified Data
Data Valid on Rising Edge of SCLK
MCLK equal to 256x Fs
23 22
SLAVE
I S 24-Bit Data
Data Valid on Rising Edge of SCLK
MCLK equal to 256x Fs
2
9
9
8
8
7
7
2
S/SPI mode is based on an internal
6
6
5
5
4
4
Right
3
3
Right
2
2
2
1
1
S compatible
CS5396 CS5397
0
0
2
S/SPI decisions is re-
DS229PP2
23 22
23 22