CS5396-KS Cirrus Logic Inc, CS5396-KS Datasheet - Page 20

• Manufacturer Part Number: CS5396-KS
• Description: ADC Dual Delta-Sigma 96KSPS 24-Bit Serial 28-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5396-KS

• Package: 28SOIC
• Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial (SPI)
• Input Type: Voltage
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar

modulators via the AINR+/- and AINL+/- pins.
Each analog input will accept a maximum of
2.0 Vpp. The + and - input signals are 180° out of
phase resulting in a differential input voltage of
4.0 Vpp. Figure 8 shows the input signal levels for
full scale.
+3.5 V
+2.5 V
+1.5 V
+3.5 V
+2.5 V
+1.5 V
The analog modulator samples the input at
6.144 MHz (MCLK=24.576 MHz) corresponding
to Fs equal to 48 kHz in the 128 Oversampling
Mode and Fs equal to 96 kHz in the 64 Oversam-
pling Mode. The digital filter will reject signals
within the stopband of the filter. However, there is
no rejection for input signals which are
(n
where n=0,1,2,...A 39
analog input and a 6.8 nF COG capacitor between
the inputs will attenuate any noise energy at
6.144 MHz, in addition to providing the optimum
source impedance for the modulators. The use of
capacitors which have a large voltage coefficient
(such as general purpose ceramics) must be avoid-
ed since these can degrade signal linearity. If active
circuitry precedes the ADC, it is recommended that
the above RC filter is placed between the active cir-
cuitry and the AINR and AINL pins. The above ex-
ample frequencies scale linearly with output
sample rate.
The on-chip voltage reference and the common
mode voltage are available at VREF and VCOM
for the purpose of decoupling only. However, due
20
Full Scale Input level= (AIN+) - (AIN-)= 4.0 Vpp
6.144 MHz) ± the digital passband frequency,
Figure 8. Full scale input voltage
resistor in series with the
AIN+
AIN-
CS5396/97
to the sensitivity of this node, the circuit traces at-
tached to these pins must be minimal in length and
no load current may be taken from VREF. It is pos-
sible to use VCOM as a reference voltage to bias
the input buffer circuits, if the circuit trace is very
short and VCOM is buffered at the converter (refer
to the CDB53965/97). The recommended decou-
pling scheme for VREF, Figure 1, is a 470 µF elec-
trolytic capacitor and a 0.1 µF ceramic capacitor
connected from VREF to AGND. The recommend-
ed decoupling scheme for VCOM, Figure 1, is a
100 µF electrolytic capacitor and a 0.1 µF ceramic
capacitor connected from VCOM to AGND.
GROUNDING AND POWER SUPPLY
DECOUPLING - ALL MODES
As with any high resolution converter, the ADC re-
quires careful attention to power supply and
grounding arrangements if its potential perfor-
mance is to be realized. Figure 1 shows the recom-
mended power arrangements, with VA and VL
connected to a clean +5 V supply. VD, which pow-
ers the digital filter, should be run from the system
+5 V logic supply, provided that it is not excessive-
ly noisy (< ±50 mV pk-to-pk). Decoupling capaci-
tors should be as near to the ADC as possible, with
the low value ceramic capacitor being the nearest.
The printed circuit board layout should have sepa-
rate analog and digital regions and ground planes,
with the ADC straddling the boundary. All signals,
especially clocks, should be kept away from the
VREF pin in order to avoid unwanted coupling into
the modulators. The VREF decoupling capacitors,
particularly the 0.01 F, must be positioned to min-
imize the electrical path from VREF and pin 3,
AGND. The CDB5396/97 evaluation board dem-
onstrates the optimum layout and power supply ar-
rangements, as well as allowing fast evaluation of
the ADC.
To minimize digital noise, connect the ADC digital
outputs only to CMOS inputs.
CS5396 CS5397
DS229PP2