M38517F8FP Renesas Electronics America, M38517F8FP Datasheet - Page 15

• Manufacturer Part Number: M38517F8FP
• Description: MCU 8-Bit 740 CISC 32KB Flash 5V 42-Pin SSOP
• Manufacturer: Renesas Electronics America

Specifications of M38517F8FP

• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Operating Temperature: -20 to 85 °C
• Number Of Timers: 4

3851 Group
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 7 I/O port function
Note: When reading bit 5, 6, or 7 of ports P3 and P4, the contents are undefined.
Rev.1.01
P0
P0
P0
P0
P0
P1
P2
P2
P2
P2
P2
P2
P2
P2
P3
P4
P4
P4
P4
P4
0
1
2
3
4
0
0
1
2
3
4
5
6
7
0
0
1
2
3
4
/S
/S
/S
/S
–P0
–P1
/X
/X
/SDA
/SCL
/SDA
/SCL
/S
/CNTR
/AN
/CNTR
/INT
/INT
/INT
/INT
IN2
OUT2
CLK2
RDY2
COUT
CIN
CLK1
Pin
0
7
7
0
1
2
3
–P3
1
2
1
2
/S
/PWM
/TxD
/RxD
0
1
CMP2
Oct 15, 2003
/S
4
/AN
RDY1
(Built-in 24 KB or more ROM)
4
Port P0
Port P1
Port P2
Port P3
Port P4
Name
page 13 of 89
Input/Output
Input/output,
individual
bits
CMOS compatible
input level
CMOS 3-state
output
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting I
BUS interface function)
CMOS 3-state output
N-channel open-drain
output (when selecting I
BUS interface function)
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting I
BUS interface function)
N-channel open-drain
output
CMOS compatible
input level
CMOS 3-state output
I/O Structure
2
2
2
C-
C-
C-
I
function I/O
Serial I/O1 function I/O
Serial I/O1 function I/O
Timer X function I/O
A-D conversion input
Timer Y function I/O
External interrupt input
External interrupt input
S
External interrupt input
PWM output
Serial I/O2 function I/O
Sub-clock generating
circuit
I
function I/O
Serial I/O1 function I/O
2
2
CMP2
C-BUS interface
C-BUS interface
Non-Port Function
output
CPU mode register
Serial I/O2 control register
I
Serial I/O1 control register
Serial I/O1 control register
Timer XY mode register
A-D control register
Timer XY mode register
I
Serial I/O1 control register
Interrupt edge selection
register
Interrupt edge selection register
PWM control register
Interrupt edge selection register
Serial I/O2 control register
2
2
C control register
C control register
Related SFRs
Ref.No.
(13)
(12)
(14)
(15)
(16)
(17)
(10)
(11)
(18)
(5)
(1)
(2)
(3)
(4)
(6)
(7)
(8)
(9)