M38517F8FP Renesas Electronics America, M38517F8FP Datasheet - Page 41

• Manufacturer Part Number: M38517F8FP
• Description: MCU 8-Bit 740 CISC 32KB Flash 5V 42-Pin SSOP
• Manufacturer: Renesas Electronics America

Specifications of M38517F8FP

• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Operating Temperature: -20 to 85 °C
• Number Of Timers: 4

3851 Group
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I
• I
• I
• I
• I
• I
• I
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generat-
2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flag
3. Use “STA $2B, STX $2B” or “STY $2B” of the zero page ad-
4. Execute the branch instruction of Item 2 and the store instruc-
Rev.1.01
2
C-BUS interface are described below.
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RWB) at the above timing.
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
The read-modify-write instruction can be executed for this regis-
ter.
0030
The read-modify-write instruction can be executed for this regis-
ter.
Precautions when using multi-master I
BUS interface
ing procedure are described in Items 2 to 5 below.
BUSFREE:
BUSBUSY:
confirming and branch process.
dressing instruction for writing the slave address value to the
I
tion of Item 3 continuously, as shown in the procedure example
above.
2
2
2
2
2
2
2
C data shift register (S0: address 002B
C address register (S0D: address 002C
C status register (S1: address 002D
C control register (S1D: address 002E
C clock control register (S2: address 002F
C START/STOP condition control register (S2D: address
LDA —
SEI
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
STA S0
LDM #$F0, S1
CLI
CLI
C data shift register.
16
•
•
•
•
•
•
•
•
•
)
Oct 15, 2003
(Built-in 24 KB or more ROM)
(Taking out of slave address value)
(Interrupt disabled)
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
(Interrupt enabled)
page 39 of 89
16
)
16
16
16
)
)
)
16
)
2
C-
5. Disable interrupts during the following three process steps:
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions for the proce-
2. Select the slave receive mode when the PIN bit is “0”. Do not
3. The SCL pin is released by writing the slave address value to
4. Disable interrupts during the following two process steps:
(4) Writing to I
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simulta-
neously. Because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1”. Because it
may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I
tus register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. Because the
STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
• Write slave address value
• Trigger RESTART condition generation
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
dure are described in items 2 to 4 below.)
Execute the following procedure when the PIN bit is “0”.
write “1” to the PIN bit. Neither “0” nor “1” is specified as input to
the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
the I
LDM #$00, S1
LDA —
SEI
STA S0
LDM #$F0, S1
CLI
2
C data shift register.
•
•
•
•
•
•
2
C status register
2
C data shift register S0 and the I
(Select slave receive mode)
(Take out of slave address value)
(Disable interrupt)
(Write slave address value)
(Trigger RESTART condition generation)
(Enable interrupt)
2
C sta-