M38517F8FP Renesas Electronics America, M38517F8FP Datasheet - Page 49

• Manufacturer Part Number: M38517F8FP
• Description: MCU 8-Bit 740 CISC 32KB Flash 5V 42-Pin SSOP
• Manufacturer: Renesas Electronics America

Specifications of M38517F8FP

• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Operating Temperature: -20 to 85 °C
• Number Of Timers: 4

3851 Group
When the middle-speed mode automatic switch set bit is set to “1”
while operating in the low-speed mode, by detecting the rising/fall-
ing edge of the SCL or SDA pin, X
and the mode is automatically switched to the middle-speed
mode. The timing which changes from the low-speed mode to the
middle-speed mode can be set as 4.5 to 5.5 cycle, or 6.5 to 7.5
cycle in the low-speed mode by the middle-speed mode automatic
switch waiting time set bit. Select according to the oscillation start
characteristic of the X
Fig. 55 System clock generating circuit block diagram (Single-chip mode)
Rev.1.01
Notes on middle-speed mode automatic
switch set bit
Oct 15, 2003
N o t e s 1 : A n y o n e o f h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 7 a n d 6 o f t h e C P U m o d e r e g i s t e r .
(Built-in 24 KB or more ROM)
I n t e r r u p t d i s a b l e f l a g l
2 : W h e n b i t 0 o f M I S R G = “ 0 ”
I n t e r r u p t r e q u e s t
W h e n l o w - s p e e d m o d e i s s e l e c t e d , s e t p o r t X c s w i t c h b i t ( b 4 ) t o “ 1 ” .
X
IN
C I N
oscillator to be used.
X
IN
Q
page 47 of 89
S
R
R e s e t
IN
X
“ 1 ”
C O U T
oscillation automatically starts
X
S T P i n s t r u c t i o n
OUT
P o r t X
s w i t c h b i t
“ 0 ”
M a i n c l o c k s t o p b i t
H i g h - s p e e d o r
m i d d l e - s p e e d
m o d e
M a i n c l o c k d i v i s i o n r a t i o
s e l e c t i o n b i t s ( N o t e 1 )
C
Low-speed mode
W I T i n s t r u c t i o n
1 / 2
l o w - s p e e d m o d e
H i g h - s p e e d o r
1 / 4
R
S
1/2
Q
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Fig. 54 Structure of MISRG
b 7
N o t e : W h e n t h e m o d e i s a u t o m a t i c a l l y s w i t c h e d f r o m t h e l o w - s p e e d m o d e t o
Timer 12 count source
selection bit
Q
t h e m i d d l e - s p e e d m o d e , t h e v a l u e o f C P U m o d e r e g i s t e r ( a d d r e s s 0 0 3 B
c h a n g e s .
S
R
P r e s c a l e r 1 2
FF
S T P i n s t r u c t i o n
16
T i m i n g
b 0
M I S R G
( M I S R G : a d d r e s s 0 0 3 8
O s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r S T P i n s t r u c t i o n
r e l e a s e d b i t
0 : A u t o m a t i c a l l y s e t “0 1
1 : A u t o m a t i c a l l y s e t n o t h i n g
M i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h s e t b i t
0 : N o t s e t a u t o m a t i c a l l y
1 : A u t o m a t i c s w i t c h i n g e n a b l e
M i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h w a i t t i m e s e t b i t
0 : 4 . 5 t o 5 . 5 m a c h i n e c y c l e s
1 : 6 . 5 t o 7 . 5 m a c h i n e c y c l e s
M i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h s t a r t b i t
( D e p e n d i n g o n p r o g r a m )
0 : I n v a l i d
1 : A u t o m a t i c s w i t c h s t a r t
N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d )
“ F F
( i n t e r n a l c l o c k )
1 6
T i m e r 1
” t o P r e s c a l e r 1 2
01
16
R e s e t o r
S T P i n s t r u c t i o n
( N o t e 2 )
R e s e t
1 6
1 6
)
” t o T i m e r 1 ,
1 6
)