M38517F8FP Renesas Electronics America, M38517F8FP Datasheet - Page 19

• Manufacturer Part Number: M38517F8FP
• Description: MCU 8-Bit 740 CISC 32KB Flash 5V 42-Pin SSOP
• Manufacturer: Renesas Electronics America

Specifications of M38517F8FP

• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Operating Temperature: -20 to 85 °C
• Number Of Timers: 4

3851 Group
INTERRUPTS
Interrupts occur by 17 : seven external, nine internal, and one soft-
ware.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
2. The interrupt disable flag is set and the corresponding interrupt
3. The interrupt jump destination address is read from the vector
Rev.1.01
register are automatically pushed onto the stack.
request bit is cleared.
table into the program counter.
Oct 15, 2003
(Built-in 24 KB or more ROM)
page 17 of 89
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
•When switching interrupt sources of an interrupt vector address
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge select bit or the interrupt source select
(3) Set the corresponding interrupt request bit to “0” after 1 or
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Related register: Interrupt edge selection register (address 003A
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 003A
Notes
bit.
more instructions have been executed.
Timer XY mode register (address 0023
16
)
16
16
)
)