M38517F8FP Renesas Electronics America, M38517F8FP Datasheet - Page 35

• Manufacturer Part Number: M38517F8FP
• Description: MCU 8-Bit 740 CISC 32KB Flash 5V 42-Pin SSOP
• Manufacturer: Renesas Electronics America

Specifications of M38517F8FP

• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Operating Temperature: -20 to 85 °C
• Number Of Timers: 4

3851 Group
[I
The I
terface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
Set “0000
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned,
this bit is set to “1”. Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
“0” by executing a write instruction to the I
(address 002B
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0”, this bit is set to “1” when a general call
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives con-
trol data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
(1) In the slave receive mode, when the 7-bit addressing format is
(2) In the slave receive mode, when the 10-bit addressing format
(3) This bit is set to “0” by executing a write instruction to the I
•Bit 3: Arbitration lost detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1”. At the same time, the TRX bit is set to “0”, so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0”. The arbitration lost
can be detected only in the master transmission mode. When ar-
bitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and ad-
dress data transmitted by another master device.
Rev.1.01
General call: The master transmits the general call address “00
Arbitration lost :The status in which communication as a master is dis-
2
•
•
•
C Status Register (S1)] 002D
selected, this bit is set to “1” in one of the following conditions:
condition agrees with the slave address stored in the high-or-
der 7 bits of the I
A general call is received.
is selected, this bit is set to “1” with the following condition:
When the address data is compared with the I
ister (8 bits consisting of slave address and RWB bit), the first
bytes agree.
data shift register (address 002B
reset.
The address data immediately after occurrence of a START
2
C status register (address 002D
2
” to the low-order 4 bits, because these bits become the
Oct 15, 2003
slaves.
16
abled.
(Built-in 24 KB or more ROM)
).
2
C address register (address 002C
page 33 of 89
16
16
) when ES0 is set to “1” or
) controls the I
2
16
C data shift register
2
C address reg-
2
C-BUS in-
16
).
16
” to all
2
C
•Bit 4: SCL pin low hold bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0”. At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (in-
cluding the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0”, the SCL is kept in the “0” state and
clock generation is disabled. Figure 33 shows an interrupt request
signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
• Executing a write instruction to the I
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ-
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately af-
• In the slave reception mode, with ALS = “1” and immediately af-
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0”, this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins
input signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
condition setting bits (SSC4–SSC0) of the I
control register (address 0030
control register (address 002E
to “0”.
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Gen-
erating Method” described later.
dress 002B
the internal clock is released and data can be communicated ex-
cept for the start condition detection.)
ing when arbitration lost is detected)
ter completion of slave address agreement or general call
address reception
ter completion of address data reception
16
). (This is the only condition which the prohibition of
16
16
) is “0” or reset, the BB flag is set
). When the ES0 bit of the I
2
C data shift register (ad-
2
C start/stop condition
2
C