ATTINY861A-XU Atmel, ATTINY861A-XU Datasheet - Page 12
ATTINY861A-XU
Manufacturer Part Number
ATTINY861A-XU
Description
Microcontrollers (MCU) 8K Flash;125B EEPROM 128B SRAM;16 IO Pins
Manufacturer
Atmel
Datasheet
1.ATTINY861A-XU.pdf
(292 pages)
Specifications of ATTINY861A-XU
Core
RISC
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-20
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY861A-XUR
Manufacturer:
IDT
Quantity:
1 300
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4.5.1
4.6
12
Instruction Execution Timing
ATtiny261A/461A/861A
SPH and SPL — Stack Pointer Register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-4
vard architecture and the fast access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 4-4.
Figure 4-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 4-5.
2nd Instruction Execute
Register Operands Fetch
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
15
SP15
SP7
7
R/W
R/W
RAMEND
RAMEND
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
clk
clk
CPU
CPU
14
SP14
SP6
6
R/W
R/W
RAMEND
RAMEND
13
SP13
SP5
5
R/W
R/W
RAMEND
RAMEND
CPU
T1
T1
, directly generated from the selected clock source for the
12
SP12
SP4
4
R/W
R/W
RAMEND
RAMEND
11
SP11
SP3
3
R/W
R/W
RAMEND
RAMEND
T2
T2
RAMEND
10
SP10
SP2
2
R/W
R/W
RAMEND
T3
T3
9
SP9
SP1
1
R/W
R/W
RAMEND
RAMEND
8
SP8
SP0
0
R/W
R/W
RAMEND
RAMEND
8197B–AVR–01/10
T4
T4
SPH
SPL
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