ATTINY861A-XU Atmel, ATTINY861A-XU Datasheet - Page 45

• Manufacturer Part Number: ATTINY861A-XU
• Description: Microcontrollers (MCU) 8K Flash;125B EEPROM 128B SRAM;16 IO Pins
• Manufacturer: Atmel

Specifications of ATTINY861A-XU

• Core: RISC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details

8.5
8.5.1
8.5.2
8197B–AVR–01/10
Register Description
MCUSR – MCU Status Register
WDTCR – Watchdog Timer Control Register
The MCU Status Register provides information on which reset source caused an MCU Reset.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the
Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed
instead of a reset if a timeout in the Watchdog Timer occurs.
If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful
for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared,
Bit
0x34 (0x54)
Read/Write
Initial Value
Bit
0x21 (0x41)
Read/Write
Initial Value
7
WDIF
R/W
0
7
–
R
0
6
WDIE
R/W
0
6
–
R
0
5
WDP3
R/W
0
5
–
R
0
4
WDCE
R/W
0
4
–
R
0
3
WDE
R/W
X
3
WDRF
R/W
See Bit Description
2
WDP2
R/W
0
2
BORF
R/W
1
WDP1
R/W
0
1
EXTRF
R/W
0
WDP0
R/W
0
0
PORF
R/W
WDTCR
MCUSR
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