LPC1776FBD208,551 NXP Semiconductors, LPC1776FBD208,551 Datasheet - Page 82
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LPC1776FBD208,551
Manufacturer Part Number
LPC1776FBD208,551
Description
IC MCU 32BIT 256KB FLASH 208LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheet
1.LPC1774FBD208551.pdf
(117 pages)
Specifications of LPC1776FBD208,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
165
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-7568
LPC1776FBD208,551
LPC1776FBD208,551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1776FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 15.
C
[1]
[2]
[3]
[4]
[5]
LPC178X_7X
Objective data sheet
Symbol
t
t
t
BLSLBLSH
BLSHEOW
BLSHDNV
Fig 16. External static memory read/write access (PB = 0)
L
= 30 pF, T
Parameters are shown as RD
Parameters specified for 40 % of V
Latest of address valid, CS LOW, OE LOW, BS LOW (PB = 1).
After End Of Read (EOR): Earliest of CS HIGH, OE HIGH, BLSx HIGH (PB = 1), address invalid.
End Of Write (EOW): Earliest of address invalid, CS HIGH, BLSx HIGH (PB = 1).
BLSx
WE
OE
CS
Dynamic characteristics: Static external memory interface
Parameter
BLS LOW to BLS HIGH time WR
BLS HIGH to end of write
time
BLS HIGH to data invalid
time
A
D
amb
=
40
[1]
C to 85
n
or WD
C, V
RD
RD
DD(IO)
2
DD(REG)(3V3)
n
1
RD
in
for rising edges and 60 % of V
Figure 16
5
Conditions
WR
WR12;
PB = 0
All information provided in this document is subject to legal disclaimers.
RD
10
11
RD
; PB = 0
; PB = 0
5
RD
= 3.0 V to 3.6 V. Values guaranteed by design.
5
as indicated in the Conditions column.
4
Rev. 2 — 27 May 2011
[1]
[5]
EOR
Min
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
cy(clk)
RD
RD
6
7
DD(IO)
+ <tbd>
WR
WR
for falling edges.
2
…continued
9
32-bit ARM Cortex-M3 microcontroller
WR
Typ
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
WR
cy(clk)
1
10
+ <tbd>
WR
12
WR
11
LPC178x/7x
Max
(WAITWR
WAITWEN + 1)
T
<tbd>
<tbd>
EOW
cy(clk)
© NXP B.V. 2011. All rights reserved.
WR
+ <tbd>
002aag214
8
82 of 117
Unit
ns
ns
ns