LPC1776FBD208,551 NXP Semiconductors, LPC1776FBD208,551 Datasheet - Page 88
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LPC1776FBD208,551
Manufacturer Part Number
LPC1776FBD208,551
Description
IC MCU 32BIT 256KB FLASH 208LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheet
1.LPC1774FBD208551.pdf
(117 pages)
Specifications of LPC1776FBD208,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
165
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-7568
LPC1776FBD208,551
LPC1776FBD208,551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1776FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC178X_7X
Objective data sheet
Table 22.
T
[1]
[2]
[3]
[4]
Symbol
T
t
t
t
t
DS
DH
v(Q)
h(Q)
amb
Fig 22. SSP master timing in SPI mode
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
T
T
SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in
the SSP clock prescale register).
T
T
T
=
cy(clk)
cy(clk)
amb
cy(clk)
amb
40
= 40 C to 85 C; V
= 25 C; V
= (SSPCLKDIV (1 + SCR) CPSDVSR) / f
is a function of the main clock frequency f
= 12 T
MOSI
MISO
MOSI
MISO
Dynamic characteristics: SSP pins in SPI mode
C to 85
Parameter
clock cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
All information provided in this document is subject to legal disclaimers.
cy(PCLK)
DD
= 3.3 V.
C, V
.
DD(REG)(3V3)
DATA VALID
Rev. 2 — 27 May 2011
DATA VALID
DD(REG)(3V3)
t
v(Q)
DATA VALID
T
DATA VALID
Conditions
in SPI mode
in SPI mode
cy(clk)
= 3.0 V to 3.6 V. Values guaranteed by design.
= 3.0 V to 3.6 V.
t
v(Q)
t
DS
DATA VALID
DATA VALID
main
main
, the SSP peripheral clock divider (SSPCLKDIV), the
t
clk(H)
t
. 2The clock cycle time derived from the SPI bit rate
t
DH
DS
32-bit ARM Cortex-M3 microcontroller
[3]
[3][4]
[3][4]
[3][4]
[3][4]
DATA VALID
DATA VALID
Min
120
14.8
2
-
2.4
t
clk(L)
t
DH
t
h(Q)
Typ
-
10.5
1
4.0
0.2
LPC178x/7x
t
h(Q)
© NXP B.V. 2011. All rights reserved.
Max
-
-
-
6.3
-
CPHA = 1
CPHA = 0
002aae829
88 of 117
Unit
ns
ns
ns
ns
ns