LX16EVK01/NOPB National Semiconductor, LX16EVK01/NOPB Datasheet - Page 33
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LX16EVK01/NOPB
Manufacturer Part Number
LX16EVK01/NOPB
Description
KIT EVAL FOR DS92LX1621/22
Manufacturer
National Semiconductor
Datasheet
1.DS92LX1621SQENOPB.pdf
(42 pages)
Specifications of LX16EVK01/NOPB
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
GENERAL PURPOSE I/O (GPIO)
The DS92LX1621 / DS92LX1622 has up to 6 GPIO (2 dedi-
cated and 4 programmable). GPIO[0] and GPIO[1] are always
available and GPIO[2:5] are available depending on the par-
allel data bus size. DIN/ROUT[0:3] can be programmed into
GPIOs (GPIO[2:5]) when the parallel data bus is less than 12
bits wide (10-bit data + HS,VS). Each GPIO can be configured
as either an input or output port. The GPIO maximum switch-
ing rate is up to 66 kHz when configured for communication
between Deserializer GPI to Serializer GPO. Whereas data
flow configured for communication between Serializer GPI to
Deserializer GPO is limited by the maximum data rate of the
PCLK.
FIGURE 28. Synchronizing Multiple Cameras
FIGURE 29. GPIO Delta Latency
33
AT-SPEED BIST (BISTEN, PASS)
An optional AT SPEED Built in Self Test (BIST) feature sup-
ports at speed testing of the high-speed serial and the bidi-
rectional control channel link. Control pins at the Deserializer
are used to enable the BIST test mode and allow the system
to initiate the test and set the duration. A HIGH on PASS pin
indicates that all payloads received during the test were error
free during the BIST duration test. A LOW on this pin at the
conclusion of the test indicates that one or more payloads
were detected with errors.
The BIST duration is defined by the width of BISTEN. BIST
starts when Deserializer LOCK goes HIGH and BISTEN is set
HIGH. BIST ends when BISTEN goes LOW. Any errors de-
tected after the BIST Duration are not included in PASS logic.
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