LX16EVK01/NOPB National Semiconductor, LX16EVK01/NOPB Datasheet - Page 6

• Manufacturer Part Number: LX16EVK01/NOPB
• Description: KIT EVAL FOR DS92LX1621/22
• Manufacturer: National Semiconductor

Specifications of LX16EVK01/NOPB

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

www.national.com
LVCMOS PARALLEL INTERFACE
ROUT[13:0]
HSYNC
VSYNC
PCLK
General Purpose Input Output (GPIO)
ROUT[3:0] /
GPIO[5:2]
GPIO[1:0]
SERIAL CONTROL BUS - I
SCL
SDA
M/S
CAD
CONTROL AND CONFIGURATION
PDB
LOCK
PASS
RES
BIST MODE
BISTEN
PASS
Channel Link III INTERFACE
DS92LX1622 Deserializer Pin Descriptions
Pin Name
9, 10, 11, 12, 14,
20, 21, 22, 23, 24
31
15, 17, 18, 19,
21, 22, 23, 24
32, 33, 39
Pin No.
26, 27
40
29
28
37
31
7
6
5
3
2
1
2
C COMPATIBLE
Input, LVCMOS w/
pull up
Output, LVCMOS
Input/Output, Digital
Input/Output, Digital
Input/Output, Digital
Input/Output, Open
Outputs, LVCMOS
Input, LVCMOS w/
Input, LVCMOS w/
Output, LVCMOS
Output, LVCMOS
Output, LVCMOS
Output, LVCMOS
Output, LVCOMS
Input, analog
I/O, Type
pull down
pull down
Drain
-
Parallel data outputs.
Parallel data output 14, typically used as Horizontal SYNC output
Parallel data output 14, typically used as Vertical SYNC output
Pixel Clock Output Pin.
Strobe edge set by RRFB control register
ROUT[3:0] general-purpose pins can be individually configured as either
inputs or outputs; used to control and respond to various commands.
General-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to V
Data line for serial control bus communication
SDA requires an external pull-up resistor to V
I
M/S = L, Master; device generates and drives the SCL clock line
M/S = H, Slave (default); device accepts SCL clock input
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection)
Power down Mode Input Pin.
PDB = H, Receiver is enabled and is ON.
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in
the SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is
shutdown and IDD is minimized.
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
When BISTEN = L; Normal operation
PASS is high to indicate no errors are detected. The PASS pin asserts low
to indicate a CRC error was detected on the link.
Reserved.
Pin 39: This pin MUST be tied LOW.
Pins 32, 33: Leave pin open.
BIST Enable Pin.
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
2
C Mode Select
6
Description
DDIO
DDIO
.
.