LX16EVK01/NOPB National Semiconductor, LX16EVK01/NOPB Datasheet - Page 4

• Manufacturer Part Number: LX16EVK01/NOPB
• Description: KIT EVAL FOR DS92LX1621/22
• Manufacturer: National Semiconductor

Specifications of LX16EVK01/NOPB

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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LVCMOS PARALLEL INTERFACE
DIN[13:0]
HSYNC
VSYNC
PCLK
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/
GPIO[5:2]
GPIO[1:0]
SERIAL CONTROL BUS - I
SCL
SDA
M/S
CAD
CONTROL AND CONFIGURATION
PDB
RES
Channel Link III INTERFACE
DOUT+
DOUT-
Power and Ground
VDDPLL
VDDT
VDDCML
VDDD
VDDIO
VSS
DS92LX1621 Serializer Pin Descriptions
Pin Name
32, 31, 30, 29,
27, 26, 24, 23,
22, 21, 20, 19,
20, 19, 18, 17
Pin No.
18, 17
16, 15
DAP
13
12
10
11
14
28
25
1
2
3
4
5
8
6
9
7
2
C COMPATIBLE
Input, LVCMOS w/
pull down
Input, analog
Input/Output, Digital DIN[3:0] general-purpose pins can be individually configured as either inputs
Input/Output, Digital General-purpose pins can be individually configured as either inputs or
Input/Output, Digital
Inputs, LVCMOS w/
Inputs, LVCMOS w/
Inputs, LVCMOS w/
Input/Output, Open
Input, LVCMOS w/
Input, LVCMOS w/
Input, LVCMOS w/
Input/Output, CML
Input/Output, CML
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
Ground, DAP
I/O, Type
pull down
pull down
pull down
pull down
pull down
pull down
Drain
Parallel data inputs.
Parallel data input 14, typically used as Horizontal SYNC Input
Parallel data input 15, typically used as Vertical SYNC Input
Pixel Clock Input Pin. Strobe edge set by TRFB control register.
or outputs; used to control and respond to various commands.
outputs; used to control and respond to various commands.
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to V
Data line for the serial control bus communication
SDA requires an external pull-up resistor to V
I
M/S = L, Master (default); device generates and drives the SCL clock line
M/S = H, Slave; device accepts SCL clock input
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
Power down Mode Input Pin.
PDB = H, Transmitter is enabled and is ON.
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in
the SLEEP state, the PLL is shutdown, and IDD is minimized.
Reserved. This pin MUST be tied LOW.
Non-inverting differential output, back-channel input.
Inverting differential output, back-channel input.
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
LVDS & BC Dr Power, 1.8V ±5%
Digital Power, 1.8V ±5%
Power for input stage, The single-ended inputs are powered from V
DAP must be grounded. Connect to ground plane with at least 9 vias.
2
C Mode Select
4
Description
DDIO
DDIO
.
.
DDIO
.