P87C54X2FBD NXP Semiconductors, P87C54X2FBD Datasheet - Page 24

• Manufacturer Part Number: P87C54X2FBD
• Description: MCU 8-Bit 87C 80C51 CISC 16KB EPROM 5V 44-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P87C54X2FBD

• Package: 44LQFP
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 33 MHz
• Ram Size: 256 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 32
• Interface Type: UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

output function line of P3.1. SHIFT CLOCK is low during S3, S4, and
Philips Semiconductors
More About Mode 0
Serial data enters and exits through RxD. TxD outputs the shift
clock. 8 bits are transmitted/received: 8 data bits (LSB first). The
baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or
1/6 the oscillator frequency (6-clock mode).
Figure 14 shows a simplified functional diagram of the serial port in
Mode 0, and associated timing.
Transmission is initiated by any instruction that uses SBUF as a
destination register. The “write to SBUF” signal at S6P2 also loads a
1 into the 9th position of the transmit shift register and tells the TX
Control block to commence a transmission. The internal timing is
such that one full machine cycle will elapse between “write to SBUF”
and activation of SEND.
SEND enables the output of the shift register to the alternate output
function line of P3.0 and also enable SHIFT CLOCK to the alternate
S5 of every machine cycle, and high during S6, S1, and S2. At
2003 Jan 24
Mode 1, 3 Max
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Mode 0 Max
Mode 2 Max
RI
SM2
REN
TB8
RB8
TI
SM0
Where SM0, SM1 specify the serial port mode, as follows:
Mode 1, 3
Mode
0
0
1
1
SCON
SM1
0
1
0
1
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be
activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not
received. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0,
RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other
modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other
modes, in any serial reception (except see SM2). Must be cleared by software.
Bit Addressable
Mode
Address = 98H
12-clock mode
3
0
1
2
Baud Rate
1.67 MHz
104.2 k
19.2 k
625 k
137.5
9.6 k
4.8 k
2.4 k
1.2 k
110
110
Description
shift register
8-bit UART
9-bit UART
9-bit UART
6-clock mode
Figure 13. Timer 1 Generated Commonly Used Baud Rates
3.34 MHz
208.4 k
1250 k
38.4 k
19.2 k
9.6 k
4.8 k
2.4 k
SM0
275
220
220
7
Figure 12. Serial Port Control (SCON) Register
Baud Rate
f
variable
f
variable
OSC
OSC
SM1
6
/12 (12-clock mode) or f
/64 or f
SM2
5
OSC
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.986 MHz
/32 (12-clock mode) or f
20 MHz
20 MHz
20 MHz
12 MHz
REN
6 MHz
f
f
4
OSC
24
TB8
the MSB of the data byte is at the output position of the shift register,
S6P2 of every machine cycle in which SEND is active, the contents
of the transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When
then the 1 that was initially loaded into the 9th position, is just to the
left of the MSB, and all positions to the left of that contain zeros.
This condition flags the TX Control block to do one last shift and
then deactivate SEND and set T1. Both of these actions occur at
S1P1 of the 10th machine cycle after “write to SBUF.”
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2
of the next machine cycle, the RX Control unit writes the bits
11111110 to the receive shift register, and in the next clock phase
activates RECEIVE.
RECEIVE enable SHIFT CLOCK to the alternate output function line
of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of
every machine cycle. At S6P2 of every machine cycle in which
RECEIVE is active, the contents of the receive shift register are
3
OSC
RB8
/6 (6-clock mode)
2
SMOD
SMOD
OSC
TI
1
X
1
1
1
0
0
0
0
0
0
0
/32 or f
RI
0
OSC
P80C3xX2; P80C5xX2;
C/T
X
X
0
0
0
0
0
0
0
0
0
/16 (6-clock mode)
Reset Value = 00H
Mode
X
X
2
2
2
2
2
2
2
2
1
Timer 1
P87C5xX2
Reload Value
FEEBH
FDH
FDH
1DH
FFH
FAH
F4H
E8H
72H
Product data
X
X
SU01626