P87LPC760BDH NXP Semiconductors, P87LPC760BDH Datasheet - Page 44

• Manufacturer Part Number: P87LPC760BDH
• Description: MCU 8-Bit 87LP 80C51 CISC 1KB EPROM 5V 14-Pin TSSOP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC760BDH

• Package: 14TSSOP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Program Memory Size: 1 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 12
• Interface Type: I2C/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

Philips Semiconductors
instructions that can be executed before the watchdog overflows
may be quite small.
Watchdog Reset
If a watchdog reset occurs, the internal reset is active for
approximately one microsecond. If the CPU clock was still running,
2002 Mar 07
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
WDCON
BIT
WDCON.7, 6
WDCON.5
WDCON.4
WDCON.3
WDCON.2–0 WDS2–0
RC OSCILLATOR
Address: A7h
Not Bit Addressable
500 kHz
CLOCK OUT
WDCLK * WDTE
STATE CLOCK
ENABLE
SYMBOL
WDS2–0
WDRUN
WDOVF
WDCLK
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
—
—
7
FEED DETECT
WATCHDOG
BOF (PCON.5)
POF (PCON.4)
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Watchdog timer overflow flag. Set when a watchdog reset or timer overflow occurs. Cleared when
the watchdog is fed.
Watchdog run control. The watchdog timer is started when WDRUN = 1 and stopped when
WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1.
Watchdog clock select. The watchdog timer is clocked by CPU clock/6 when WDCLK = 1 and by
the watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the watchdog RC
oscillator) if the WDTE configuration bit = 1.
Watchdog rate select.
Timeout Clocks
Reset Value:
—
6
1,048,576
131,072
262,144
524,288
WDTE + WDRUN
Figure 37. Watchdog Timer Control Register (WDCON)
16,384
32,768
65,536
8,192
Figure 36. Block Diagram of the Watchdog Timer
WDOVF
5
10h for other rest sources if the watchdog is enabled via the WDTE configuration bit.
00h for other reset sources if the watchdog is disabled via the WDTE configuration bit.
30h for a watchdog reset.
WDRUN
Minimum Time
4
165 ms
330 ms
660 ms
1.3 sec
(WDCON.2–0)
10 ms
20 ms
41 ms
82 ms
WDS2–0
WDCLK
41
CLEAR
3
20-BIT COUNTER
code execution will begin immediately after that. If the processor
was in Power Down mode, the watchdog reset will start the
oscillator and code execution will resume after the oscillator is
stable.
WDS2
8 TO 1 MUX
2
8 MSBs
Nominal Time
1.05 sec
131 ms
262 ms
524 ms
2.1 sec
16 ms
32 ms
65 ms
WDS1
1
WDS0
0
S
R
WDTE (UCFG1.7)
Maximum Time
Q
1.44 sec
180 ms
360 ms
719 ms
2.9 sec
23 ms
45 ms
90 ms
P87LPC760
(WDCON.5)
WDOVF
WATCHDOG
WATCHDOG
INTERRUPT
RESET
SU01633
Preliminary data
SU01634