P89V51RD2FN NXP Semiconductors, P89V51RD2FN Datasheet - Page 28

• Manufacturer Part Number: P89V51RD2FN
• Description: MCU 8-Bit 89V 80C51 CISC 64KB Flash 5V 40-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P89V51RD2FN

• Package: 40PDIP
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
Table 14.
Not bit addressable; Reset value: 0000 0000B; Reset source(s): any source
Table 15.
Table 16.
Table 17.
Bit addressable; Reset value: 0000 0000B; Reset source(s): any reset
Table 18.
Bit
M1
0
0
1
1
1
Bit
7
6
5
4
3
Bit
Symbol
Bit
Symbol
TMOD - Timer/counter mode control register (address 89H) bit allocation
TMOD - Timer/counter mode control register (address 89H) bit description
TMOD - Timer/counter mode control register (address 89H) M1/M0 operating
mode
TCON - Timer/counter control register (address 88H) bit allocation
TCON - Timer/counter control register (address 88H) bit description
T1GATE
Symbol
T1/T0
GATE
C/T
Symbol
TF1
TR1
TF0
TR0
IE1
TF1
M0
0
1
0
1
1
7
7
Rev. 05 — 12 November 2009
T1C/T
TR1
6
6
Description
Bits controlling Timer1/Timer0
Gating control when set. Timer/counter ‘x’ is enabled only while ‘INTx’
pin is HIGH and ‘TRx’ control pin is set. When cleared, Timer ‘x’ is
enabled whenever ‘TRx’ control bit is set.
Gating Timer or Counter Selector cleared for Timer operation (input
from internal system clock.) Set for Counter operation (input from ‘Tx’
input pin).
Description
Timer 1 overflow flag. Set by hardware on Timer/counter overflow.
Cleared by hardware when the processor vectors to Timer 1 Interrupt
routine, or by software.
Timer 1 Run control bit. Set/cleared by software to turn Timer/counter
1 on/off.
Timer 0 overflow flag. Set by hardware on Timer/counter overflow.
Cleared by hardware when the processor vectors to Timer 0 Interrupt
routine, or by software.
Timer 0 Run control bit. Set/cleared by software to turn Timer/counter
0 on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
Operating mode
0
1
2
3
3
T1M1
TF0
5
5
T1M0
8048 timer ‘TLx’ serves as 5-bit prescaler
16-bit Timer/counter ‘THx’ and ‘TLx' are cascaded;
there is no prescaler.
8-bit auto-reload Timer/counter ‘THx’ holds a value
which is to be reloaded into ‘TLx’ each time it
overflows.
(Timer 0) TL0 is an 8-bit Timer/counter controlled
by the standard Timer 0 control bits. TH0 is an 8-bit
timer only controlled by Timer 1 control bits.
(Timer 1) Timer/counter 1 stopped.
TR0
P89V51RB2/RC2/RD2
4
4
8-bit microcontrollers with 80C51 core
T0GATE
IE1
3
3
T0C/T
IT1
2
2
© NXP B.V. 2009. All rights reserved.
T0M1
IE0
1
1
T0M0
28 of 80
IT0
0
0