IS43DR16160A-25EBLI ISSI, Integrated Silicon Solution Inc, IS43DR16160A-25EBLI Datasheet - Page 24

• Manufacturer Part Number: IS43DR16160A-25EBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43DR16160A-25EBLI

• Lead Free Status / Rohs Status: Compliant

IS43/46DR83200A, IS43/46DR16160A
DDR2-400/533 tDS1/tDh1 derating with single-ended data strobe
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet
tDS(base) and tDH(base) value to the DtDS and DtDH derating value respectively. Example: tDS (total setup time) =
tDS(base) + DtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and
the first crossing of Vih(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal
slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is
later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line
to the actual signal from the ac level to dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and
the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the
last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew
rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(dc) level is used for derating value.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/
IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach
VIH/IL(ac).
For slew rates in between the values listed in the "Data Setup and Hold Time Derating" tables, the derating values
may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
24
DQ
Slew
rate
V/ns
DtDS1, DtDH1 derating values for DDR2-400, DDR2-533 (All units in ‘ps’; the note applies to the entire table)
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1 DtDS1 DtDH1
188
146
2.0 V/ns
63
-
-
-
-
-
-
167
167
125
-
-
-
-
-
-
145
125
1.5 V/ns
42
31
-
-
-
-
-
125
125
83
69
-
-
-
-
-
-11
-25
1.0 V/ns
63
83
0
-
-
-
-
-14
-31
42
0
-
-
-
-
-
-13
-27
-45
0.9 V/ns
81
-2
-
-
-
-
DQS, Single-ended Slew Rate
-13
-30
-53
43
1
-
-
-
-
-18
-32
-50
-74
0.8 V/ns
-7
-
-
-
-
Integrated Silicon Solution, Inc. — www.issi.com
-13
-27
-44
-67
-96
-
-
-
-
-128 -156 -145 -180 -175 -223 -226 -288
-29
-43
-61
-85
0.7 V/ns
-
-
-
-
-114 -102 -138 -132 -181 -183 -246
-45
-62
-85
-
-
-
-
-210 -243 -240 -286 -291 -351
-60
-78
0.6 V/ns
-
-
-
-
-109 -108 -152
-86
-
-
-
-
0.5 V/ns
-
-
-
-
-
-
-
-
-
-
0.4 V/ns
-
-
-
-
-
-
05/24/2011
Rev. B
-
-
-
-
-
-