IS43DR16160A-25EBLI ISSI, Integrated Silicon Solution Inc, IS43DR16160A-25EBLI Datasheet - Page 26

• Manufacturer Part Number: IS43DR16160A-25EBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43DR16160A-25EBLI

• Lead Free Status / Rohs Status: Compliant

IS43/46DR83200A, IS43/46DR16160A
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet
tIS(base) and tIH(base) value to the DtIS and DtIH derating value respectively. Example: tIS (total setup time) =
tIS(base) + DtIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and
the first crossing of Vih(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal
slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is
later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line
to the actual signal from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and
the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal
slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(dc) level is used for derating value.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/
IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach
VIH/IL(ac).
For slew rates in between the values listed in the "Input Setup and Hold Time Derating" tables, the derating values
may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
26
Command/
Address
Slew rate
(V/ns)
0.25
0.15
3.5
2.5
1.5
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
4
3
2
1
DtIS and DtIH Derating Values for DDR2-667, DDR2-800
-1000
-100
-168
-200
-325
-517
DtIS
150
143
133
120
100
-13
-22
-34
-60
67
-5
0
2.0 V/ns
-1125
DtIH
-125
-188
-292
-375
-500
-708
-14
-31
-54
-83
94
89
83
75
45
21
0
CK,CK Differential Slew Rate
-138
-170
-295
-487
-970
DtIS
180
173
163
150
130
-30
-70
97
30
25
17
-4
8
1.5 V/ns
-1095
DtIH
-158
-262
-345
-470
-678
124
119
113
105
-24
-53
-95
75
51
30
16
-1
Integrated Silicon Solution, Inc. — www.issi.com
-108
-140
-265
-457
-940
DtIS
210
203
193
180
160
127
-40
60
55
47
38
26
0
1.0 V/ns
-1065
DtIH
-128
-232
-315
-440
-648
154
149
143
135
105
-23
-65
81
60
46
29
6
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
05/24/2011
Rev. B