DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 157
![IC TXRX T1/E1/J1 1-CHIP 100-LQFP](/photos/6/82/68291/406-100-lqfp_sml.jpg)
DS2156L+
Manufacturer Part Number
DS2156L+
Description
IC TXRX T1/E1/J1 1-CHIP 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2156L.pdf
(265 pages)
Specifications of DS2156L+
Function
Single-Chip Transceiver
Interface
E1, J1, T1, TDM, UTOPIA II
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0, 1/Receive Termination Select (RT0, RT1)
Bits 2, 3/Transmit Termination Select (TT0, TT1)
Bits 4, 5/MCLK Prescaler for T1 Mode
Bits 4, 5/MCLK Prescaler for E1 Mode
Bit 6/CMI Invert (CMII)
Bit 7/CMI Enable (CMIE)
RT1
TT1
0
0
1
1
0
0
1
1
MCLK
MCLK
(MHz)
12.352
16.384
(MHz)
16.384
1.544
3.088
6.176
2.048
4.096
8.192
2.048
4.096
8.192
0 = CMI normal at TTIP and RTIP
1 = invert CMI signal at TTIP and RTIP
0 = disable CMI mode
1 = enable CMI mode
RT0
TT0
CMIE
0
1
0
1
0
1
0
1
7
0
MPS1
MPS1
Internal receive-side termination disabled
Internal receive-side 75Ω enabled
Internal receive-side 100Ω enabled
Internal receive-side 120Ω enabled
Internal transmit-side termination disabled
Internal transmit -side 75Ω enabled
Internal transmit -side 100Ω enabled
Internal transmit -side 120Ω enabled
Internal Transmit-Termination Configuration
Internal Receive-Termination Configuration
0
0
1
1
0
0
1
1
0
0
1
1
CMII
LIC4
Line Interface Control 4
7Bh
6
0
MPS0
MPS0
MPS1
0
1
0
1
0
1
0
1
0
1
0
1
5
0
MPS0
JAMUX
(LIC2.3)
JAMUX
(LIC2.3)
4
0
0
0
0
0
1
1
1
1
0
0
0
0
157 of 265
TT1
3
0
TT0
2
0
RT1
1
0
RT0
0
0
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