DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 185
![IC TXRX T1/E1/J1 1-CHIP 100-LQFP](/photos/6/82/68291/406-100-lqfp_sml.jpg)
DS2156L+
Manufacturer Part Number
DS2156L+
Description
IC TXRX T1/E1/J1 1-CHIP 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2156L.pdf
(265 pages)
Specifications of DS2156L+
Function
Single-Chip Transceiver
Interface
E1, J1, T1, TDM, UTOPIA II
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit HEC-Insertion Enable (THIE)
Bit 1/Transmit HEC Error-Insertion Enable (THEIE)
Bit 2/Transmit COSET-Addition Enable (TCAE)
Bit 3/Transmit Cell-Rate Decoupling Selection (TCRDS)
Bit 4/Transmit Payload-Scrambling Enable (TPSE)
Bits 5 to 7/Unassigned, must be set to 0 for proper operation
0 = HEC byte as received from ATM layer is transparently passed
1 = proper HEC value is computed and inserted in the HEC byte of the cell
0 = HEC error insertion disabled
1 = HEC errors introduced in the transmitted cells as specified by transmit HEC error-insertion pattern
register
0 = no COSET addition
1 = COSET (0x55) addition to the calculated HEC
Note that if HEC insertion is disabled, then the HEC byte is transmitted transparently (this bit does not
impact ATM layer cells). However, the HEC byte of idle/unassigned cells used for cell-rate decoupling
includes COSET addition as long as the TCAE bit is enabled.
0 = idle cell
1 = unassigned cell
0 = disabling scrambling
1 = enabling scrambling
—
7
0
—
U_TCR1
UTOPIA Transmit Control Register 1
56h
6
0
—
5
0
TPSE
4
0
185 of 265
TCRDS
3
0
TCAE
2
1
THEIE
1
0
THIE
0
1
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