DS2156L+ Maxim Integrated Products, DS2156L+ Datasheet - Page 186
![IC TXRX T1/E1/J1 1-CHIP 100-LQFP](/photos/6/82/68291/406-100-lqfp_sml.jpg)
DS2156L+
Manufacturer Part Number
DS2156L+
Description
IC TXRX T1/E1/J1 1-CHIP 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2156L.pdf
(265 pages)
Specifications of DS2156L+
Function
Single-Chip Transceiver
Interface
E1, J1, T1, TDM, UTOPIA II
Number Of Circuits
1
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
BERT Generator and Detector, CMI Coder and Decoder, HDLC Controller
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0, 2, 6, 7/Unassigned, must be set to 0 for proper operation
Bit 1/Transmit Physical-Layer Interface Mode (TPLIM)
Bit 3/Transmit Clear E1 Selection (TCES). When this bit is set = 0, TS16 and TS0 are automatically gapped out.
This is only meaningful when U_TCR2.1 is set = 0. E1TCR1.7 must be set = 1 if TCES = 1.
Bits 4, 5/Transmit FIFO Depth Configuration Bits (FDC1, FDC0)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Port Configuration (RPC)
Bit 1/Receive UTOPIA Polling Mode (RUPM)
Bits 2 to 7/Unassigned, should be set to 0 for proper operation
FDC1
0
0
1
1
0 = clock + data + frame-pulse indication combination
1 = gapped clock + data combination
0 = TS16 and TS0 gapped out
1 = TS16 and TS0 not gapped out
0 = T1 mode
1 = E1 mode
0 = multiplexed with 1CLAV mode
1 = direct status
FDC0
—
—
7
7
0
0
0
1
0
1
—
—
U_TCR2
UTOPIA Transmit Control Register 2
57h
U_RCFR
UTOPIA Receive Configuration Register
60h
6
0
6
0
Cell Depth
Reserved
4
3
2
FDC1
—
5
0
5
0
FDC0
—
4
0
4
0
186 of 265
TCES
—
3
0
3
0
—
—
2
0
2
0
TPLIM
RUPM
1
0
1
0
RPC
—
0
0
0
0
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