IDT75P52100S100BX IDT, Integrated Device Technology Inc, IDT75P52100S100BX Datasheet

IDT75P52100S100BX

Manufacturer Part Number

IDT75P52100S100BX

Description

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT75P52100S100BX.pdf (3 pages)

Specifications of IDT75P52100S100BX

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 2003 Integrated Device Technology, Inc.

Device Description

(NSEs) and a comprehensive suite of software that enable and accelerate

the intelligent processing of network services in communications equip-

ment. As a part of the complete IDT classification subsystem that includes

content inspection engines, the IDT family of NSEs delivers high-

performance, feature-rich, easy-to-use, integrated search accelerators.

synchronous full-ternary 64K x 72 entry device. Each entry location in

the NSE has both a Data entry and an associated Mask entry. The NSE

devices integrate content addressable memory (CAM) technology with

high-performance logic. The device can perform Lookup and Learn NSE

operations plus Read, Write, Burst Write, and Dual Write maintenance

operations.

multiplexed address and data bus that can support 100 million sustained

searches per second. This device provides array segments which can

be configured to enable multiple width lookups from 36 to 576 bits wide.

The IDT 75P52100 requires a 1.8-volt V

or 2.5-volt V

provides the user with flexibility and control in determining the device

power. Only the array segments that will be used for a specific NSE

operation are powered up while the unused segments are not.

CMOS processing technology and is packaged in a JEDEC Standard,

thermally enhanced, low profile Ball Grid Array. The options include a

304 BGA, satisfying smaller footprint requirements and a 372 BGA

package that is compatible with IDT's 32K x 72 Entry (75P42100) and

128K x 72 Entry (75P62100) NSE devices.

System Configurations

networking systems. In solutions requiring data searching such as

routers, a system configuration as shown in Figure 1.0 may be realized.

Maximum flexibility is provided by allowing one board design to be

populated today using either the IDT 75P42100 or 75P52100 NSEs and

later upgraded to use IDT’s 75K62100 NSE. Applications note AN-279

discusses how to accommodate one board design for any of these NSEs.

ASIC/ FPGA for lookups and routes an Index to an associated SRAM

device, which supplies the next hop address via an SRAM Data Bus to

the ASIC. The NSE provides the required control signals to directly

hookup to ZBT™ or Synchronous Pipeline Burst SRAM. Lookup results

can also be fed directly back to the ASIC/ FPGA without the use of external

SRAM. Control of the associated handshake signals is provided by all

NSEs to adapt to either configuration.

IDT provides proven, industry-leading network search engines

The IDT 75P52100 NSE is a high performance pipelined low-power,

The IDT 75P52100 NSE device has a bi-directional bus that is a

The IDT 75P52100 utilizes IDT’s latest high-performance 1.8V

The IDT NSEs are designed to fulfill the needs of various types of

In this compatible configuration, the NSE interfaces directly to an

To request the full IDT75P52100 datasheet, please contact your local

DDQ

supply, and a 2.5-volt V

IDT Sales Representative or call 1-800-345-7015

BIAS

supply, a user selectable 1.8

supply. This NSE device

NETWORK SEARCH ENGINE

64K x 72 Entries

Product specifications subject to change without notice.

Figure 1.0 ASIC / Compatible NSE / SRAM configuration

REQUEST

Block Diagram

NSE

BUS

LAST SRAM

LAST NSE

PHASE

BURST

CLOCK

RESET

Command

Request

REQSTB

Data

Bus

Counter

÷ 2

FPGA

ASIC

Instruction

Address

Bypass

DATA

CCLK

Network Search Engine

R/W

75K62100

75P42100

75P52100

Global Mask Registers

Comparand Registers

Result Register

IDT

Configuration Registers

ARRAY

Ram Control Circuits

and

5333 drw 01

Datasheet

Sync SRAM

75P52100

Optional

JUNE 2003

ZBT

SRAM CONTROL

ASIC FEEDBACK

5333 drw02

Index

MATCHOUT

MMOUT

Bus

DSC-5333/03

Brief

RESPONSE

NSE

BUS

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IDT75P52100S100BX Summary of contents

Page 1

... ASIC. The NSE provides the required control signals to directly hookup to ZBT™ or Synchronous Pipeline Burst SRAM. Lookup results can also be fed directly back to the ASIC/ FPGA without the use of external SRAM. Control of the associated handshake signals is provided by all NSEs to adapt to either configuration. ...

Page 2

... The NSE Response Bus is comprised of an independent unidirec- tional Index Bus which drives the result of the lookup (or index) to either an SRAM device or an ASIC. In addition to driving the Index, the NSE Response Bus also drives the associated SRAM control signals (CE/OE, and WE) for either ZBT™ or Synchronous Pipeline Burst SRAM devices. ...

Page 3

... This bus is used to drive the address of an external SRAM, or feedback Lookup result information directly to the NSE's ASIC/FPGA. The Index Bus contain the encoded location at which the compare was found, the address of the NSE which found the result and the Lookup type. ...

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