SI3200-BS Silicon Laboratories Inc, SI3200-BS Datasheet
SI3200-BS
Specifications of SI3200-BS
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SI3200-BS Summary of contents
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... IC performs all high voltage functions and operates from a 3 supply as well as single or dual battery supplies up to 100 V. The Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is available in a thermally enhanced 16-pin small outline (SOIC) package. ...
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... Si3220/Si3225 Dual ProSLIC Selection Guide Part Description Number Si3200-KS Linefeed interface Si3200-BS Linefeed interface Si3220-KQ Dual ProSLIC Si3220-BQ Dual ProSLIC Si3225-KQ Dual ProSLIC Si3225-BQ Dual ProSLIC 2 On-Chip External Pulse Metering Ringing Ringing Support " " " " " " Preliminary Rev. 0.91 ...
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... General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8-Bit Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16-Bit RAM Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Pin Descriptions: Si3220/ 101 Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Preliminary Rev ...
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... Si3220/Si3225 Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter Supply Voltage, Si3200 and Si3220/ Si3225 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 TIP or RING Voltage, Si3205 TIP, RING Current, Si3200 STIPAC, STIPDC, SRINGAC, SRINGDC Current, Si3220/Si3225 ...
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... Supply Voltage, Si3220/Si3225 Supply Voltage, Si3200 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Table 3 ...
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... Si3220/Si3225 Table 3. 3.3 V Power Supply Characteristics ( – °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter Symbol V Supply Current I BAT VBAT (Si3200) Power Consumption P SLEEP P OPEN P STBY P STBY P ACTIVE P ACTIVE P OHT P OHT P RING *Note: All specifications are for a single channel based on measurements with both channels in the same operating state. ...
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... Supply Current I DD VDD (Si3200) V Supply Current I BAT VBAT (Si3200) *Note: All specifications are for a single channel based on measurements with both channels in the same operating state. * Test Condition Sleep mode, RESET = 0 VDD4 Open (high-impedance) Active on-hook standby Forward/reverse active off-hook ABIAS = 4 mA ...
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Si3220/Si3225 Table Power Supply Characteristics ( – °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter Symbol Power Consumption P SLEEP P ...
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Table 5. AC Characteristics ( –V = 3. °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter Overload Level Overload Compression 1 Single Frequency Distortion ...
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Si3220/Si3225 Table 5. AC Characteristics (Continued –V = 3. °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter 5 Transhybrid Balance 6 Idle Channel ...
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Table 6. Linefeed Characteristics ( –V = 3. °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A Parameter Symbol Maximum Loop Resistance R LOOP DC Loop ...
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... DD4 A Parameter Symbol Differential Nonlinearity DNLE (8-bit resolution) Integral Nonlinearity INLE (8-bit resolution) Gain Error Table 8. Si3200 Characteristics (V = 3. °C for K-Grade, – °C for B-Grade Parameter TIP/RING Pulldown Transistor Saturation Voltage TIP/RING Pullup Transistor Satu- ration Voltage Battery Switch Saturation Imped- ...
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Table 9. DC Characteristics ( – DD1 DD4 A Parameter Symbol High Level Input V IH Voltage Low Level Input V IL Voltage High Level Output V OH Voltage ...
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Si3220/Si3225 Table 11. Switching Characteristics—General Inputs ( –V = 3. °C for K-Grade, – °C for B-Grade DD1 DD4 A Parameter Rise Time, RESET 2 RESET ...
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SCLK CS SDI SDO Table 13. Switching Characteristics—PCM Highway Interface ( –V = 3. °C for K-Grade, – °C for B-Grade DD1 DD4 A Parameter PCLK ...
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Si3220/Si3225 Table 13. Switching Characteristics—PCM Highway Interface (Continued –V = 3. °C for K-Grade, – °C for B-Grade DD1 DD4 A Parameter Delay Time, PCLK ...
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Table 14. Switching Characteristics—GCI Highway Serial Interface ( –V = 3. °C for K-Grade, – °C for B-Grade) DD DD1 DD4 A 1 Parameter PCLK Period (2.048 MHz ...
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Si3220/Si3225 PCLK t su1 FSYNC Frame 0, DRX Bit 0 DTX Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) Acceptable Region Figure 5. Transmit and Receive Path SNDR ...
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Fundamental 5 Output Power (dBm0 2 Figure 6. Overload Compression Performance 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 ...
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Si3220/Si3225 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 ...
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TX Group Delay Distortion 1100 1000 900 800 700 600 500 400 300 200 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 Frequency (Hz) Figure 9. Transmit Group Delay ...
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Transmit Path Decimation + A/D Filter Codec Loopback DLM3 Interpolation D buf m From Billing Tone DAC Receive Path Figure 11. AC Signal Path Block Diagram for a Single Channel Decimation + THPF ...
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... RPIb R18 182 15 RPOb R15 806k 16 SVBATb R11 402k C11 0.1u 100V R13 4.7k X7R C12 0.1u 100V R14 4.7k X7R VDD R12 402k U3 Si3200 1 16 TIP ITIPP ITIPN 3 14 RING THERM 4 13 VBAT IRINGP 5 12 VBATH IRINGN 6 11 VBATL BATSWb ...
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... NC ITIPN 3 14 RING THERM 4 13 VBAT IRINGP 5 12 VBATH IRINGN 6 11 VBATL GND NC R16 40. VDD BATSEL C33 0.1u epad Si3200 GND 100V VBLO RNGNGb R21 RNGNGa 510 VRNGSOURCE R9 R20 806k 806k VDD J2 TRD1a 1 TRD1a 2 J3 TRD2a 1 TRD2a RRDa RRDa 47 /CS ...
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... R6, R16 40.2 kΩ, 1/10 W, ±5% 182 Ω, 1/10 W, ±1% R7, R8, R17, R18 R10 40.2 kΩ, 1/10 W, ±1% Table 16. Si3225 + Si3200 External Component Values Component C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% 1 µF, 6.3 V, X7R, ±20% ...
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... The Si3220 and Si3225 are available in a 64-lead TQFP and the Si3200 is available in a 16-lead SOIC. Dual ProSLIC Architecture The Dual ProSLIC chipset is comprised of a low-voltage CMOS device that uses a low-cost integrated linefeed ...
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... DC OV RING; Capacitor C the TIP and RING leads to be measured. The Si3220 and Si3225 both use the Si3200 to drive TIP and RING and isolate the high-voltage line from the low-voltage CMOS devices. The Si3220 and Si3225 measure voltage at various nodes to monitor the linefeed current. R provide these measuring points ...
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... Figure 15. Simplified Dual ProSLIC Linefeed Architecture for TIP and RING Leads (diagram illustrates either TIP or RING lead of a single channel) 28 Low Frequency Diagnostic Filters Monitor A/D A/D DSP D/A SLIC DAC Σ SLIC Control Loop Si3200 Battery Current Select Mirror Control Preliminary Rev. 0.91 Si3220/ Si3225 SLIC Control V Sense BAT R BAT ...
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... Monitoring and Power Fault Detection" on page 33 for Open (LF[2:0] = 000). The Si3200 output is high-impedance. This mode can be used in the presence of line fault conditions and to generate open switch intervals (OSIs). The device also can automatically enter the Open state if excess power consumption is detected in the Si3200. ...
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Si3220/Si3225 Table 18. Register and RAM Locations for Linefeed Control Parameter Register/RAM Mnemonic Linefeed LINEFEED Linefeed Shadow LINEFEED Battery Feed Control RELAYCON Loop Current Limit ILIM On-Hook Line Voltage VOC Common Mode Voltage VCM V Delta for Off-Hook VOCDELTA OC ...
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Loop Closure = 640 Ω Threshold Constant 30 TIP-RING Voltage Region LIM (mA) LOOP Figure 16. V vs. I Characteristic for TIP–RING LOOP ...
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Si3220/Si3225 Only one calibration should be necessary if the system remains powered up. To optimize performance recommended that the user perform the following steps when running the CAL routines: 1. Set CALR1 = 0x3F and CALR2 = 0x3E. ...
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... Si3200 die temperature data to the Si3220/3225. The Dual ProSLIC devices also have the ability to prevent thermal overloads by regulating the total power inside the Si3200 or in each of the external bipolar transistors (if using a discrete linefeed circuit). The DSP engine performs all power calculations and ...
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... IRQVEC3 register are set when a power alarm is triggered in the respective transistor. When using the , the thermal Si3200, the PQ1E bit enables the power alarm interrupt, and the PQ1S bit is set when a Si3200 power alarm is triggered. 4096 × thermal Preliminary Rev. 0.91 ...
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... IRQVEC3 PQ1S–PQ6S IRQEN3 PQ1E–PQ6E The Dual ProSLIC devices rely on the Si3200 to power the line from the battery supply. The PCB layout and enclosure conditions should be designed to allow sufficient thermal dissipation out of the Si3200, and a programmable power alarm threshold ensures product safety under all operating conditions. See " ...
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Si3220/Si3225 provided in Table 21. The primary input to the system is the loop current sense value from the voltage/current/ power monitoring circuitry and reported in the ILOOP RAM address. The LCS value is processed in the input signal processor ...
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Table 21. Register and RAM Locations Used for Loop Closure Detection (Continued) Loop Closure Threshold (on- hook to off-hook) Loop Closure Threshold (off- hook to on-hook) Loop Closure Filter Coefficient Loop Closure Mask Interval Notes calculated ...
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Si3220/Si3225 Table 22. Register and RAM Locations Used for Ground Key Detection Parameter Register/ Mnemonics Ground Key Interrupt IRQVEC2 Pending Ground Key Interrupt IRQEN2 Enable Ground Key Linefeed LINEFEED Shadow Ground Key Detect Status LCRRTP Ground Key Detect LONGDBI Debounce ...
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... Bits RLYCON BATSEL BATHTH BATHTH[14:7] BATLTH BATLTH[14:7] RLYCON GPO RLYCON BSEL BATLPF BATLPF[15:3] Si3220 Si3225 Battery Battery Sense Control Circuit Logic Si3200 Linefeed Circuitry V BATL V BAT V BATH Preliminary Rev. 0.91 Si3220/Si3225 Programmable Resolution Range (LSB Size) Toggle N 160.173 V* 628 mV (4.907 mV 160.173 V* 628 mV (4 ...
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... The Si3220’s BATSEL pin is used to switch between the VBATH (typically –48 V) and VBATL (typically –24 V) rails using the switch internal to the Si3200. The Si3220’s GPO pin is used along with the external transistor circuit to switch the VRING rail (the ringing voltage battery rail) onto the Si3200’ ...
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... Adding dc offset to the ringing signal decreases the maximum possible ringing amplitude. Adding significant dc offset also increases – the power dissipation in the Si3200 and may require additional airflow or modified PCB layout to maintain acceptable operating temperatures in the line feed circuitry. The Dual ProSLIC chipset automatically ...
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Si3220/Si3225 Table 25. Register and RAM Locations Used for Ringing Generation (Continued) Parameter Ringing Initial Phase Sinusoidal Trapezoid External Ringing Ringing Relay Driver Enable (Si3225 only) Ringing Overhead Voltage Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by the ...
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... If an offset of the ringing signal from the ring lead is desired, VOVR can be used for this purpose. Ringing Power Considerations The total power consumption of the Si3220/Si3200 chipset using internal ringing generation is dependent on the VDD supply voltage, the desired ringing values for amplitude, the total loop impedance, and the AC load impedance (number of REN) ...
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Si3220/Si3225 Ring Trip Detection A ring trip event signals that the terminal equipment has transitioned to an off-hook state after ringing has commenced, ensuring that the ringing signal is removed before normal speech begins. The Dual ProSLIC is designed to ...
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LFS Input Full Wave ILOOP Signal Rectifier Processor Figure 27. Ring Trip Detect Processing Circuitry RTACTH AC Ring Trip Threshold _ Debounce Filter_AC Digital + LPF RTACDB RTPER Digital + LPF _ DC Ring Trip Threshold RTDCTH Preliminary Rev. 0.91 ...
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Si3220/Si3225 Table 26. Recommended Values for Ring Trip Registers and RAM Addresses Ringing Ringing DC Method Frequency Offset Added? Yes 16– Internal (Si3220) Yes 33– External 16–32 Hz Yes (Si3225) 33–60 Hz Yes Notes: 1. All ...
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Depending on the loop length and the ring trip method, the ring trip detection circuits are disabled by setting their respective ring trip thresholds (RTACTH ...
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Si3220/Si3225 Si3220/ Si3225 Figure 29. Driving Relays with V The maximum allowable R value can be calculated with the following equation: DRV MaxR DRV Table 28. Recommended R ProSLIC V Relay V DD 3.3 V ±5% 3.3 V ±5% 5 ...
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IRINGXSCAL D ZERDELAY COUNTER0 COUNTER1 RINGEN RRD On LF LFSDELAY LFS Ringing Figure 30. Timing Characteristics for Ringing Relay Control ...
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... Figure 30 illustrates the 50 RING Protection Si3200 TIP timing sequence for a typical ringing relay control application. During a typical ringing sequence, the Si3225 monitors both the ringing relay current (IRNGNG) and the RINGEN bit of the RINGCON register ...
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Polarity Reversal The Dual ProSLIC devices support polarity reversal for message waiting functionality and various signaling modes. The ramp rate can be programmed for a smooth transition or an abrupt transition to accommodate different application requirements. A wink function is ...
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Si3220/Si3225 V (V) TIP/RING Set VOCZERO bit to 1 Figure 32. Wink Function with Programmable Ramp Rate Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to ...
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R is the series resistance caused by PROT protection devices R is the series portion of the synthesized S impedance R ||C is the parallel portion of the P P synthesized impedance The user must enter the value of R ...
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Si3220/Si3225 8 kHz Clock OSCnEN Zero 16-Bit Cross OSCnTA Modulo Logic Expire Counter OSCnTI Expire OSCnTA INT OSCnTAEN Logic OSCnTI INT OSCnTIEN Logic *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Oscillator ...
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To enable automatic cadence for tone generator 1, define the OSC1TA and OSC1TI registers and then set the OSC1TAEN and OSC1TIEN bits. This enables each of the timers to control the state of the Oscillator Enable bit, OSC1EN. The 16-bit ...
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Si3220/Si3225 OSC1EN ... ... 0,1 , OSC1TA ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Message Message Parameter 1 Type Length Message Header Parameter Type Figure 37. On-Hook Caller ID Transmission Sequence 56 ...
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Tone Generator Interrupts Both the active and inactive timers can generate an interrupt to signal “on/off” transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the OS1TAE and OS1TIE bits. Timer interrupts ...
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Si3220/Si3225 coeff – 15 × PMAMPL ----------------------- - – coeff + where Full Scale V PK The pulse metering oscillator has a volume envelope (linear ramp) on the on/off ...
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BUF A Figure 38. Pulse Metering Generation Block Diagram DTMF Detection On-chip DTMF detection, also known as Touch Tone, is available in the Si3220 and Si3225 in-band signaling system that replaces the pulse- ...
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Si3220/Si3225 Table 36. DTMF Hex Codes Digit Hex code 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 6 0x6 7 0x7 8 0x8 9 0x9 0 0xA * 0xB # 0xC A 0xD B 0xE C 0xF D ...
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TPGA or RPGA PCM where M = {0, 1/16384, 2/16384,...32767/16384} Figure 39. TPGA and RPGA structure Audio Characteristics The dominant source of distortion and noise in both the transmit and receive paths is the quantization noise introduced ...
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Si3220/Si3225 Interrupt Logic The Dual ProSLIC devices are capable of generating interrupts for the following events: ! Loop current/ring ground detected. ! Ring trip detected. ! Ground Key detected. ! Power alarm. ! DTMF digit detected. ! Active timer 1 ...
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The control byte has the following structure and is presented on the SDI pin MSB first BRDCST R/W REG/RAM Reserved The bits are defined as follows: 7 BRDCST Indicates a broadcast operation that is intended for all devices ...
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Si3220/Si3225 Channel 0 CS SDO Channel 1 Channel 2 CS SDO Channel 3 Channel 14 CS SDO Channel 15 Figure 41. SPI Daisy-Chain Mode Preliminary Rev. 0.91 SDI0 SDI SDI1 Dual P ...
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In Figure 42 the CID field this field is decremented (in LSB to MSB order) the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes ...
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Si3220/Si3225 Figures 43 and 44 illustrate WRITE and READ operations to register addresses via an 8-bit SPI controller. These operations are performed as a 3-byte transfer asserted between each byte which is required for asserted ...
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Figures 45 and 46 illustrate WRITE and READ operations to register addresses via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The absence of CS going high after the eighth bit of data ...
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Si3220/Si3225 CS SCLK SDI CONTROL SDO Figure 49. RAM Write Operation via a 16-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 50. RAM Read Operation via a 16-Bit SPI Port 68 ADDRESS Data [15:8] ADDRESS Data [15:8] Preliminary Rev. ...
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PCM Interface The Dual ProSLIC devices programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled by the PCLK and FSYNC inputs, PCM Mode Select, PCM Transmit Start PCMTXLO), and PCM Receive Start Count ...
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Si3220/Si3225 PCM Companding The Dual ProSLIC devices support both µ-255 Law (µ- Law) and A-Law companding formats in addition to Linear Data mode. The data format is selected via the PCMF bits of the PCM Mode Select register. µ-Law mode ...
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Table 38. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Si3220/Si3225 Table 39. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 ...
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General Circuit Interface The Dual ProSLIC devices also contain an alternate communication interface to the SPI and PCM control and data interface. The general circuit interface (GCI) is used for the transmission and reception of both control and data information ...
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Si3220/Si3225 Indicate (C/I) bits and two handshaking bits, MR and MX. The C/I bits indicate status and command communication, while the handshaking bits Monitor Receive (MR) and Monitor Transmit (MX), exchange data in the Monitor channel. Figure 55 illustrates the ...
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FS CH0 Sub-Frame 16 B1 Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode Monitor Channel The Monitor channel is used for initialization and setup of the Dual ProSLIC devices also for general communication with the Dual ...
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Si3220/Si3225 The Idle state is achieved by the MX and MR bits being held inactive for two or more frames. When a transmission is initiated by a host device, an active state is seen on the downstream MX bit. This ...
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Idle Rec eiv alid New ...
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Si3220/Si3225 Idle RQT RQT RQT nth ...
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M onitor Da ta Dow nstre a m $FF $FF $91 $91 $81 $81 $10 µ 125 s 1 Frame M X Dow nstre a m Bit M R Dow nstre a m Bit M onitor Da ta Upstre a ...
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M onitor Da ta Dow nstre a m $FF $FF $91 $91 $01 $01 $10 µ 125 s 1 Frame M X Dow nstre a m Bit M R Dow nstre a m Bit M onitor Da ta Upstre a ...
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Programming the Dual ProSLIC Using the Monitor Channel The Dual ProSLIC devices use the monitor channel to Transfer Status or Operating mode information to and from the host processor. Communication with the Dual ProSLIC should be in the following format: ...
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Si3220/Si3225 SC Channel The downstream and upstream SC channels are continuously carrying I/O information to and from the Dual ProSLIC during every frame. The upstream processor has immediate access to the receive (downstream) and transmit (upstream) data present on the ...
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... The transition to the OPEN state stemming from power alarm detection is intended to protect the Dual ProSLIC circuit in the event that too much power is dissipated in the Si3200 LFIC. This alarm is typically due to a fault in the application circuit or on the subscriber loop, but can be caused by intermittent power spikes depending on the threshold to which the alarm is set ...
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Si3220/Si3225 cycles. If the Dual ProSLIC continues to automatically transition to the OPEN state, the power alarm threshold might be set incorrectly. If this problem persists after the power alarm settings are verified, a system fault is Table 45. Automatic ...
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System Testing The Dual ProSLIC devices include a complete suite of test tools to test the functionality of the line card and detect fault conditions present on the TIP/RING pair. Using one of the loopback test modes with the signal ...
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Si3220/Si3225 Table 47. Summary of Signal Generation and Measurement Tools Function DC Current Generation DC Voltage Generation Audio Tone Generation Ringing Signal Generation 8-Bit DC/Low Frequency Monitor A/D Converter Programmable Timer AC Low Pass Filter 16-Bit Audio A/D Converter Transmit ...
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VTIP VRING VLOOP VLONG ILOOP ILONG VRING,EXT IRING,EXT Figure 64. SLIC Diagnostic Filter Structure Measurement Tools ! 8-Bit monitor A/D converter. This 8-bit A/D converter monitors all dc and low frequency voltage and current data from TIP to ground and ...
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Si3220/Si3225 ! Programmable timer. The Dual ProSLIC devices incorporate several digital oscillator circuits to program the on- and off-times of the ringing and pulse metering signals. The tone generation oscillator can be used to program a time period for averaging ...
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Line capacitance measurement. Implemented like the ac line impedance measurement test above, but the frequency band of interest is between 1 kHz and 3.4 kHz. Knowing the synthesized 2-wire impedance of the Dual ProSLIC, the roll-off effect can be ...
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Si3220/Si3225 8-Bit Control Register Summary Any register not listed here is reserved and must not be written. Shaded registers are read only. All registers are assigned a default value during initialization and following a system reset. Only registers 0, 2, ...
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Reg Mnemonic Description 3 Addr 2 MSTREN Master Initialization Enable 3 MSTRSTAT Master Initialization Status 61 O1TAHI Oscillator 1 Active Timer— High Byte 60 O1TALO Oscillator 1 Active Timer— Low Byte 63 O1TIHI Oscillator 1 Inactive Timer— High Byte 62 ...
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... RAMDAT[15:8] RAMDAT[7:0] Soft Reset Ringing 4 4 ENSYNC RDACEN RINGUNB TAEN RINGTA[15:8] RINGTA[7:0] RINGTI[15:8] RINGTI[7:0] Relay Configuration 5 BSEL RRAIL SLIC Bias Control Si3200 Thermometer 4 STAT Tone Detection FAILCNT[3: VALID VALTONE Impedance Synthesis Coefficients COEFFA1[15:8] Preliminary Rev. 0.91 Bit 3 Bit 2 Bit 1 Bit POLREV ...
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Reg Mnemonic Description 3 Addr 47 ZA1LO Impedance Synthesis Coeff A1—Low Byte 52 ZA2HI Impedance Synthesis Coeff A2—High Byte 51 ZA2MID Impedance Synthesis Coeff A2—Middle Byte 50 ZA2LO Impedance Synthesis Coeff A2—Low Byte 37 ZB0HI Impedance Synthesis Coeff B0—High Byte ...
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Si3220/Si3225 16-Bit RAM Address Summary All internal 16-bit RAM addresses can be assigned unique values for each SLIC channel and are accessed in a similar manner as the 8-bit control registers except the data is twice as long. In addition, ...
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RAM Mnemonic Description Addr 108 DTROW0TH DTMF Row 0 Peak Threshold 109 DTROW1TH DTMF Row 1 Peak Threshold 117 DTROW2HTH DTMF Row Second Harmonic Threshold 110 DTROW2TH DTMF Row 2 Peak Threshold 111 DTROW3TH DTMF Row 3 Peak Threshold 115 ...
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Si3220/Si3225 RAM Mnemonic Description Addr 9 ILONG Longitudinal Current Sense Value 8 ILOOP Loop Current Sense Value 18 IRING Q5 Current Measurement 16 IRINGN Q3 Current Measurement 15 IRINGP Q2 Current Measurement 21 IRNGNG External Ringing Genera- tor Current Measurement ...
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RAM Mnemonic Description Addr 40 PLPFQ12 Q1/Q2 Thermal Low Pass Filter Coeff 41 PLFPQ34 Q3/Q4 Thermal Low Pass Filter Coeff 42 PLFPQ56 Q5/Q6 Thermal Low Pass Filter Coeff 68 PMAMPL Pulse Metering Amplitude 70 PMAMPTH Pulse Metering AGC Amplitude Threshold ...
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Si3220/Si3225 RAM Mnemonic Description Addr 65 RTDCDB DC Ring Trip Debounce Interval 62 RTDCTH DC Ring Trip Detect Threshold 63 RTPER Ring Trip Low Pass Filter Coeff Period 81 RXIIRPOL RX IIR Filter Pole Coeff 80 RXEQCO0 RX Equalizer Coeff ...
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RAM Mnemonic Description Addr 162 TESTAVTH TX Diag Filter Avg Threshold 126 TESTB0H1 TX Diag Filter Coeff B0H1 136 TESTB0H2 TX Diag Filter Coeff B0H2 146 TESTB0H3 TX Diag Filter Coeff B0H3 125 TESTB0L1 TX Diag Filter Coeff B0L1 135 ...
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Si3220/Si3225 RAM Mnemonic Description Addr 124 TXMODPWR TX Path Modem Tone Power 122 TXPWR TX Path Input Signal Power 13 VBAT Scaled Battery Voltage Measurement 4 VCM Common Mode Voltage 7 VLOOP Loop Voltage 0 VOC Open Circuit Voltage 1 ...
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Pin Descriptions: Si3220/ SVBATa 1 RPOa 2 RPIa 3 RNIa 4 RNOa 5 CAPPa 6 Si3220 CAPMa 7 QGND 8 64-Lead TQFP 9 IREF (epad) CAPMb 10 CAPPb ...
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... Analog current output drives dc current onto RING side of sub- scriber loop in reverse polarity. Also modulates ac current onto RING side of loop. I Temperature Sensor. Senses Internal temperature of Si3200. O Test Relay Driver Output. Drives test relays for connecting loop test equipment. No Internal Connection. Leave unconnected or connect to ground plane. ...
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Pin Number(s) Symbol Si3220 Si3225 28, 52 RTRPb, RTRPa 30, 50 30, 50 TRD2b, TRD2a 31, 48 RRDb, RRDa 31, 48 GPOb, GPOa 32, 49 32, 49 BATSELb, BATSELa 35 35 DRX 36 36 DTX 39 39 PCLK 33 33 ...
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Si3220/Si3225 Pin Number(s) Symbol Si3220 Si3225 BLKRNG epad epad GND 104 Input/ Description Output I Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, serial port is ...
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... RING Output. Connect to the RING lead of the subscriber loop. Operating Battery Voltage. Si3200 internal system battery supply. Connect SVBATa/b pin from Si3220/ 25 and decouple with a 0.1 µF/100 V filter capacitor. High Battery Voltage. Connect to the system ringing battery supply. Decouple with a 0.1 µF/100 V filter capacitor ...
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Si3220/Si3225 Pin #(s) Symbol Input/ Output 12 IRINGN I 13 IRINGP I 14 THERM O 15 ITIPN I 16 ITIPP I epad GND 106 Description Negative RING Current Control. Connect to the IRINGN lead of the Si3220 or Si3225. Positive ...
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... Dual ProSLIC Selection Guide Part Description Number Si3200-KS Linefeed interface Si3200-BS Linefeed interface Si3220-KQ Dual ProSLIC Si3220-BQ Dual ProSLIC Si3225-KQ Dual ProSLIC Si3225-BQ Dual ProSLIC On-Chip External Pulse Metering Ringing Ringing Support " " " " " " Preliminary Rev. 0.91 ...
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Si3220/Si3225 Package Outline: 64-Pin TQFP Figure 65 illustrates the package details for the Dual ProSLIC. Table 48 lists the values for the dimensions shown in the illustration See Detail ...
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... Package Outline: 16-Pin SOIC Figure 66 illustrates the package details for the Si3200. Table 49 lists the values for the dimensions shown in the illustration Seating Plane Figure 66. 16-Pin Small Outline Integrated Circuit (SOIC) Package Table 49. Package Diagram Dimensions E H θ L Exposed Pad 2.3 x 3.6 mm ...
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Si3220/Si3225 Document Change List Revision 0.9 to Revision 0.91 ! Table 8 on page 12 TIP/RING Pulldown Transistor Saturation Voltage " updated. TIP/RING Pullup Transistor Saturation Voltage updated. " Note added. " ! "Calculating Overhead Voltages" on page 27 Second ...
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Notes: Preliminary Rev. 0.91 Si3220/Si3225 111 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, ProSLIC, and Modfeed are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...