SC16IS762IPW,112 NXP Semiconductors, SC16IS762IPW,112 Datasheet - Page 35

• Manufacturer Part Number: SC16IS762IPW,112
• Description: IC DUAL UART 64BYTE 28TSSOP
• Manufacturer: NXP Semiconductors

Specifications of SC16IS762IPW,112

• Features: Low Current
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4021-5; 935279294112; SC16IS762IPW; SC16IS762IPW

NXP Semiconductors
10. I
SC16IS752_SC16IS762_7
Product data sheet
2
C-bus operation
10.1 Data transfers
The two lines of the I
lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a
microcontroller or a memory can both transmit and receive data.
One data bit is transferred during each clock pulse (see
line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP
condition (see
free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.
The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most significant bit first, and is followed by an acknowledge bit
(see
master. The device that acknowledges has to pull down the SDA line during the
acknowledge clock pulse, while the transmitting device releases this pulse (see
Figure
Fig 12. Bit transfer on the I
Fig 13. START and STOP conditions
Figure
SDA
SCL
15).
14). The clock pulse related to the acknowledge bit is generated by the
Figure
START condition
SDA
SCL
S
2
C-bus are a serial data line (SDA) and a serial clock line (SCL). Both
13). The bus is considered to be busy after the START condition and
Dual UART with I
Rev. 07 — 19 May 2008
2
C-bus
data valid
data line
stable;
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
allowed
change
of data
Figure
STOP condition
12). The data on the SDA
mba607
P
© NXP B.V. 2008. All rights reserved.
mba608
SDA
SCL
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