SC16IS762IBS,151 NXP Semiconductors, SC16IS762IBS,151 Datasheet - Page 30

• Manufacturer Part Number: SC16IS762IBS,151
• Description: IC UART DUAL I2C/SPI 32-HVQFN
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16IS762IBS,151

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: Low Current
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2240; 935279293151; SC16IS762IBS-S

NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
8.13 Transmitter FIFO Level register (TXLVL)
8.14 Receiver FIFO Level register (RXLVL)
8.15 Programmable I/O pins Direction register (IODir)
8.16 Programmable I/O pins State register (IOState)
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
Table 24.
This register is a read-only register, it reports the fill level of the receive FIFO, that is, the
number of characters in the RX FIFO.
Table 25.
This register is used to program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to
GPIO7.
Table 26.
When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each
register bit will be transferred to the corresponding I/O pin programmed as output.
Table 27.
Bit
7
6:0
Bit
7
6:0
Bit
7:0
Bit
7:0
Symbol
-
TXLVL[6:0]
Symbol
-
RXLVL[6:0]
Symbol
IODir
Symbol
IOState
Transmitter FIFO Level register bits description
Receiver FIFO Level register bits description
IODir register bits description
IOState register bits description
Dual UART with I
Rev. 07 — 19 May 2008
Description
not used; set to zeros
number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40)
Description
not used; set to zeros
number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)
Description
Set GPIO pins [7:0] to input or output.
Description
Write this register: set the logic level on the output pins
Read this register: return states of all pins
0 = input
1 = output
0 = set output pin to zero
1 = set output pin to one
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
© NXP B.V. 2008. All rights reserved.
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