SC16C752BIB48,157 NXP Semiconductors, SC16C752BIB48,157 Datasheet - Page 19
![IC UART DUAL W/FIFO 48-LQFP](/photos/6/64/66484/568-48-lqfp_sot313-2_sml.jpg)
SC16C752BIB48,157
Manufacturer Part Number
SC16C752BIB48,157
Description
IC UART DUAL W/FIFO 48-LQFP
Manufacturer
NXP Semiconductors
Type
Dual UART with 64-byte FIFOsr
Datasheet
1.SC16C752BIBS151.pdf
(47 pages)
Specifications of SC16C752BIB48,157
Number Of Channels
2, DUART
Package / Case
48-LQFP
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
4.5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1322
935274411157
SC16C752BIB48
935274411157
SC16C752BIB48
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C752BIB48,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
7. Register descriptions
SC16C752B
Product data sheet
Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table
Table 9.
[1]
[2]
[3]
[4]
[5]
[6]
A2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
Fig 13. Crystal oscillator connections
MCR[7] can only be modified when EFR[4] is set.
Accessed by a combination of address pins and register bits.
Accessible only when LCR[7] is logic 1.
Accessible only when LCR is set to 1011 1111 (BFh).
Accessible only when EFR[4] = logic 1 and MCR[6] = logic 1, i.e., EFR[4] and MCR[6] are read/write
enables.
Accessible only when CSA or CSB = logic 0, MCR[2] = logic 1, and loopback is disabled
(MCR[4] = logic 0).
9.
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
Register map - read/write properties
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
All information provided in this document is subject to legal disclaimers.
Read mode
Receive Holding Register (RHR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
Line Control Register (LCR)
Modem Control Register (MCR)
Line Status Register (LSR)
Modem Status Register (MSR)
Scratchpad Register (SPR)
Divisor Latch LSB (DLL)
Divisor Latch MSB (DLM)
Enhanced Feature Register (EFR)
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmission Control Register (TCR)
Trigger Level Register (TLR)
FIFO ready register
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 6 — 30 November 2010
XTAL1
1.8432 MHz
C1
22 pF
[2][4]
[2][4]
[2][4]
[2][4]
X1
XTAL2
[2][6]
C2
33 pF
[2][3]
[2][3]
[2][5]
[1]
[2][4]
XTAL1
[2][5]
1.8432 MHz
C1
22 pF
X1
Write mode
Transmit Holding Register (THR)
Interrupt Enable Register
FIFO Control Register (FCR)
Line Control Register
Modem Control Register
Scratchpad Register
Divisor Latch LSB
Divisor Latch MSB
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmission Control Register
Trigger Level Register
XTAL2
002aaa870
1.5 kΩ
C2
47 pF
SC16C752B
[2][4]
[2][4]
[2][4]
[2][4]
© NXP B.V. 2010. All rights reserved.
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