SC16C754BIBM,151 NXP Semiconductors, SC16C754BIBM,151 Datasheet
SC16C754BIBM,151
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SC16C754BIBM-S
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SC16C754BIBM,151 Summary of contents
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SC16C754B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Rev. 04 — 6 October 2008 1. General description The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow ...
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... NXP Semiconductors I Software (Xon/Xoff)/hardware (RTS/CTS) flow control N Programmable Xon/Xoff characters N Programmable auto-RTS and auto-CTS I Optional data flow resume by Xon any character I DMA signalling capability for both received and transmitted data I Supports 5 V, 3.3 V and 2.5 V operation I Software selectable baud rate generator ...
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... NXP Semiconductors 4. Block diagram SC16C754B DATA BUS IOR AND IOW CONTROL RESET LOGIC REGISTER SELECT CSA to CSD LOGIC INTA to INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC INTSEL Fig 1. Block diagram of SC16C754B SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 1 CTSA 2 DTRA RTSA 5 INTA 6 7 CSA 8 TXA SC16C754BIBM IOW 9 TXB 10 11 CSB INTB 12 RTSB 13 14 GND 15 DTRB CTSB 16 Pin confi ...
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... NXP Semiconductors DSRA CTSA DTRA V RTSA INTA CSA TXA IOW TXB CSB INTB RTSB GND DTRB CTSB DSRB Fig 3. SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 1 n.c. n. SC16C754BIB80 n.c. 20 Pin configuration for LQFP80 Rev. 04 — ...
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... NXP Semiconductors Fig 4. 5.2 Pin description Table 2. Pin description Symbol Pin LQFP64 LQFP80 PLCC68 CDA CDB CDC CDD CLKSEL - 26 30 SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 10 CTSA 11 DTRA RTSA 14 INTA 15 16 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin LQFP64 LQFP80 PLCC68 CSA CSB CSC CSD CTSA CTSB CTSC CTSD 53, 54, 68, 69, 66, 67, 55, 56, 70, 71, 68 57, 58, 72, 73 59, 60 74, 75 DSRA DSRB DSRC DSRD DTRA DTRB DTRC DTRD GND 14, 28, 16, 36, 6, 23, 45, 61 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin LQFP64 LQFP80 PLCC68 IOW n. 20, 31 21, 22, 27, 40, 41, 42, 60, 61, 62, 80 RESET RIA RIB RIC RID RTSA RTSB RTSC RTSD RXA RXB RXC RXD RXRDY - 34 38 TXA TXB TXC TXD TXRDY - 35 39 SC16C754B_4 Product data sheet ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin LQFP64 LQFP80 PLCC68 V 4, 21, 6, 46, 66 13, 47 XTAL1 XTAL2 Functional description The SC16C754B UART is pin-compatible with the SC16C554 and SC16C654 UARTs. It provides more enhanced features. All additional features are provided through a special enhanced feature register ...
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... NXP Semiconductors 6.2 Hardware flow control Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled/disabled independently by programming EFR[7:6]. With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and de-activates the RTS output when the RX FIFO is suffi ...
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... NXP Semiconductors 6.2.1 Auto-RTS Auto-RTS data flow control originates in the receiver block (see SC16C754B”). used in auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is de-asserted ...
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... NXP Semiconductors 6.3 Software flow control Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3. EFR[ Remark: When using software flow control, the Xon/Xoff characters cannot be used for data characters. There are two other enhanced features relating to software fl ...
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... NXP Semiconductors 6.3.2 TX Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the halt trigger level programmed in TCR[3:0]. Xon1/Xon2 character is transmitted when the RX FIFO reaches the resume trigger level programmed in TCR[7:4]. The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set characters, then the least signifi ...
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... NXP Semiconductors UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RX FIFO, but assumes the interrupt latency is fairly long. UART1 will continue sending characters until a total of 60 characters have been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt transmission ...
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... NXP Semiconductors 6.5 Interrupts The SC16C754B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 7:5 and 3:0. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0] ...
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... NXP Semiconductors 6.5.1 Interrupt mode operation In interrupt mode (if any bit of IER[3:0] is ‘1’) the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced ...
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... NXP Semiconductors 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[ DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. ...
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... NXP Semiconductors 6.6.2 Block DMA transfers (DMA mode 1) Figure 12 wrptr trigger wrptr Fig 12. TXRDY and RXRDY in DMA mode 1 6.6.2.1 Transmitter TXRDY is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. 6.6.2.2 Receiver RXRDY becomes active when the trigger level has been reached, or when a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is fl ...
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... NXP Semiconductors 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RX, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6]. ...
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... NXP Semiconductors Table 7. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 8. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 ...
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... NXP Semiconductors Fig 14. Crystal oscillator connection 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9. Table [1] MCR[7] can only be modified when EFR[4] is set. [2] Accessed by a combination of address pins and register bits. ...
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... NXP Semiconductors Table 10 Table 10. SC16C754B internal registers Register Bit 7 [1] General register set RHR bit THR bit IER 0/CTS interrupt [2] enable FCR RX trigger level (MSB IIR FCR[ LCR DLAB MCR [2] clock LSR 0/error in RX FIFO MSR SPR bit TCR bit TLR ...
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... NXP Semiconductors Remark: Refer to the notes under 7.1 Receiver Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register (LCR) ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. shows FIFO control register bit settings. Table 11. Bit 7:6 ...
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... NXP Semiconductors 7.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. shows the line control register bit settings. Table 12. Bit 1:0 ...
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... NXP Semiconductors 7.5 Line Status Register (LSR) Table 13 Table 13. Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is output directly onto the output data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identifi ...
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... NXP Semiconductors 7.6 Modem Control Register (MCR) The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 14. Bit [1] MCR[7:5] can only be modified when EFR[4] is set, that is, EFR[ write enable. SC16C754B_4 Product data sheet ...
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... NXP Semiconductors 7.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. per channel. Table 15. ...
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... NXP Semiconductors 7.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW to HIGH. The INT output signal is activated in response to interrupt generation. shows the interrupt enable register bit settings. ...
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... NXP Semiconductors 7.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17. Bit Symbol 7:6 IIR[7:6] 5 IIR[5] 4 IIR[4] 3:1 IIR[3:1] 0 IIR[0] The interrupt priority list is shown in Table 18. Priority level ...
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... NXP Semiconductors 7.10 Enhanced Feature Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. the enhanced feature register bit settings. Table 19. Bit 3:0 7.11 Divisor latches (DLL, DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLM stores the most signifi ...
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... NXP Semiconductors 7.12 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. settings. Table 20. Bit Symbol 7:4 TCR[7:4] 3:0 TCR[3:0] TCR trigger levels are available from bytes with a granularity of four. Remark: TCR can only be written to when EFR[ and MCR[ The programmer must program the TCR such that TCR[3:0] > ...
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... NXP Semiconductors The FIFO ready register is a read-only register that can be accessed when any of the four UARTs is selected CSA to CSD = 0, MCR[2] (FIFO Rdy Enable logic 1, and loopback is disabled. The address is 111. 8. Programmer’s guide The base set of registers that is used during high-speed data transfer have a straightforward access method ...
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... NXP Semiconductors Table 23. Command set TX FIFO and RX FIFO thresholds to VALUE read FIFO Rdy register set prescaler value to divide-by-1 set prescaler value to divide-by-4 [1] sign here means bit-AND. SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Register programming guide … ...
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... NXP Semiconductors 9. Limiting values Table 24. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Limiting values Parameter Conditions supply voltage voltage on any other pin ...
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... NXP Semiconductors 10. Static characteristics Table 25. Static characteristics Tolerance unless otherwise specified. CC Symbol Parameter Conditions V supply voltage CC V input voltage I V HIGH-level input IH voltage V LOW-level input IL voltage V output voltage O V HIGH-level output voltage LOW-level output [5] voltage input capacitance i T ambient operating in ...
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... NXP Semiconductors 11. Dynamic characteristics Table 26. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t pulse width LOW WL t pulse width HIGH WH f oscillator/clock frequency XTAL t address set-up time 6s t address hold time 6h t IOR delay from chip select 7d t IOR strobe width ...
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... NXP Semiconductors [1] Applies to external clock, crystal oscillator max 24 MHz. 1 -------------- - [2] Maximum frequency = t w clk [3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. [4] RESET pulse must happen when CS, IOW, IOR signals are inactive. ...
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... NXP Semiconductors active IOW RTS change of state DTR CD CTS DSR INT IOR RI Fig 17. Modem input/output timing external clock -------------- - XTAL t w clk Fig 18. External clock timing SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs t 17d ...
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... NXP Semiconductors RX INT IOR Fig 19. Receive timing RX RXRDY IOR Fig 20. Receive ready timing in non-FIFO mode SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit data bits ( data bits 6 data bits 7 data bits 16 baud rate clock ...
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... NXP Semiconductors RX RXRDY IOR Fig 21. Receive ready timing in FIFO mode TX INT active IOW Fig 22. Transmit timing SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit data bits ( start bit data bits ( data bits ...
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... NXP Semiconductors TX IOW active byte #1 t 27d TXRDY Fig 23. Transmit ready timing in non-FIFO mode TX IOW active byte #32 TXRDY Fig 24. Transmit ready timing in FIFO mode (DMA mode 1) SC16C754B_4 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs ...
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... NXP Semiconductors 12. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors LQFP80: plastic low profile quad flat package; 80 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.16 1.5 1.6 mm 0.25 0.04 1.3 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT315-1 136E15 Fig 26 ...
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... NXP Semiconductors PLCC68: plastic leaded chip carrier; 68 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.3 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.13 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 29. Acronym CPU DLL DLM DMA FIFO LSB MSB TTL UART SC16C754B_4 Product data sheet ...
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... NXP Semiconductors 15. Revision history Table 30. Revision history Document ID Release date SC16C754B_4 20081006 • Modifications: Section 2 • Table 24 “Limiting – deleted symbol V – deleted symbol V – added symbol V • Section 7.14 “FIFO Ready register (FIFO two UARTs is selected...” to “when any of the four UARTS is selected...” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 Trigger levels 6.2 Hardware flow control . . . . . . . . . . . . . . . . . . . 10 6.2.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3 Software flow control . . . . . . . . . . . . . . . . . . . 12 6.3.1 RX 6.3.2 TX ...