sc16c654 NXP Semiconductors, sc16c654 Datasheet
sc16c654
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sc16c654 Summary of contents
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... System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C654/654D operates 3.3 V and 2.5 V, and the industrial temperature range, and is available in plastic PLCC68 and LQFP64 packages. 2. Features ...
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... Even-, Odd-, or No-Parity formats 1 1 2-stop bit 2 Baud generation (DC to 1.5 Mbit/s) Loop-back controls for communications link fault isolation Rev. 04 — 19 June 2003 SC16C654/654D Version SOT188-2 10 1.4 mm SOT314-2 10 1.4 mm SOT314-2 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... A0–A2 REGISTER CSA-CSD SELECT LOGIC 16/68 INTA-INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC INTSEL Fig 1. SC16C654/654D block diagram (16 mode). 9397 750 11617 Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder TRANSMIT FIFO REGISTERS FLOW CONTROL LOGIC RECEIVE FIFO REGISTERS FLOW ...
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... CONTROL LOGIC A0–A4 REGISTER CS SELECT LOGIC 16/68 IRQ INTERRUPT TXRDY CONTROL RXRDY LOGIC Fig 2. SC16C654/654D block diagram (68 mode). 9397 750 11617 Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder TRANSMIT FIFO REGISTERS FLOW CONTROL LOGIC RECEIVE FIFO REGISTERS FLOW ...
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... RTSB 22 GND 23 DTRB 24 CTSB 25 DSRB 26 Fig 3. PLCC68 pin configuration (16 mode). 9397 750 11617 Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder SC16C654IA68 16 MODE Rev. 04 — 19 June 2003 SC16C654/654D 60 DSRD 59 CTSD 58 DTRD 57 GND 56 RTSD 55 INTD 54 CSD 53 TXD 52 IOR ...
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... RTSB 22 GND 23 DTRB 24 CTSB 25 DSRB 26 Fig 4. PLCC68 pin configuration (68 mode). 9397 750 11617 Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder SC16C654IA68 68 MODE Rev. 04 — 19 June 2003 SC16C654/654D 60 DSRD 59 CTSD 58 DTRD 57 GND 56 RTSD TXD 52 NC ...
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... I Address 0 select bit. Internal registers address selection in 16 and 68 modes. I Address 1 select bit. Internal registers address selection in 16 and 68 modes. I Address 2 select bit. Internal registers address selection in 16 and 68 modes. Rev. 04 — 19 June 2003 SC16C654/654D 48 DSRD 47 CTSD 46 DTRD 45 ...
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... Clear to Send (Active-LOW). These inputs are associated with individual UART channels A through D. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16C654/654D. Status can be tested by reading MSR[4]. This pin only affects the transmit or receive operations when Auto CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware fl ...
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... MCR[3] is set to a logic 1 to enable the 3-State outputs. This pin is disabled in the 68 mode. Due to pin limitations on the 64-pin packages, this pin is not available. To cover this limitation, the SC16C654DIB64 version operates in the continuous interrupt enable mode by bonding this pin to V SC16C654IB64 operates with MCR[3] control by bonding this pin to GND. ...
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... I Receive data input RXA-RXD. These inputs are associated with individual serial channel data to the SC16C654/654D. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX input internally ...
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... SC16C654/654D is downward compatible with the 16C454/554 or the 68C454/554, dependent on the state of the interface mode selection pin, 16/68. The SC16C654/654D is capable of operation to 1.5 Mbits/s with a 24 MHz crystal and Mbits/s with an external clock input (at 3.3 V and 2.5 V the max speed is 3 Mbits/s). With a crystal of 14.7464 MHz, and through a software option, the user can select data rates up to 460 ...
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... In the 16 mode, INTSEL and MCR[3] can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations of the 64-pin package, this feature is offered by two different LQFP64 packages. The SC16C654D operates in the continuous interrupt enable mode by bonding INTSEL to V internally. The SC16C654 operates in conjunction with MCR[3] by bonding CC INTSEL to GND internally ...
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... Philips Semiconductors 6.4 Internal registers The SC16C654/654D provides 15 internal registers for monitoring and control. These registers are shown in in the standard 16C554. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR) ...
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... IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters’ values, the SC16C654/654D will monitor the receive data stream for a match to the Xon1,2 character value(s match is found, the SC16C654/654D will resume operation and clear the fl ...
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... In the event that the receive buffer is overfilling and flow control needs to be executed, the SC16C654/654D automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The SC16C654/654D sends the Xoff1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the SC16C654/654D will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level ...
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... Fig 6. Crystal oscillator connection. The generator divides the input 16 clock by any divisor from SC16C654/654D divides the basic external clock by 16. Further division of this 16 clock provides two table rates to support low and high data rate applications using the 9397 750 11617 ...
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... Philips Semiconductors same system design. After a hardware reset and during initialization, the SC16C654/654D sets the default baud rate table according to the state of the CLKSEL pin. A logic 1 on CLKSEL will set the 1 clock default, whereas logic 0 will set the 4 clock default table. Following the default clock rate selection during initialization, the rate tables can be changed by the internal register MCR[7] ...
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... RX, RI, CTS, DSR, CD transmit data is provided by the user. If the sleep mode is enabled and the SC16C654/654D is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user ...
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... RECEIVE RECEIVE SHIFT FIFO REGISTER REGISTERS FLOW CONTROL LOGIC MODEM CONTROL CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 04 — 19 June 2003 SC16C654/654D TXA-TXD IR ENCODER RXA-RXD IR DECODER RTSA-RTSD DSRA-DSRD DTRA-DTRD CTSA-CTSD LOGIC OP1A-OP1D RIA-RID OP2A-OP2D CDA-CDD 002aaa209 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF 9397 750 11617 Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder details the assigned bit functions for the SC16C654/654D internal registers. Bit 7 Bit 6 Bit 5 Bit 4 ...
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... FIFO full; logic least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C654/654D and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
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... FIFO reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C654/654D in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • ...
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... Logic 0 = Set DMA mode ‘0’ (normal default condition). Logic 1 = Set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C654/654D is in the 16C450 mode (FIFOs disabled; FCR[0] = logic the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0 ...
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... FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C654/654D is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 when the trigger level has been reached. ...
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... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C654/654D provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... Logic 0 or cleared = default condition. LCR[1-0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Logic 0 or cleared = default condition. Rev. 04 — 19 June 2003 SC16C654/654D Table 16). Table 17). Table 18). ...
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... The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode, the infrared TX output will be a logic 0 during idle data conditions. Rev. 04 — 19 June 2003 SC16C654/654D Section 6.11 generator”. © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... MCR[4] Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16C654/654D I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C654/654D and the CPU. Table 20: Bit 9397 750 11617 Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder Line Status Register bits description ...
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... A modem Status Interrupt will be generated. [1] MSR[2] RI Logic change (normal default condition). Logic 1 = The RI input to the SC16C654/654D has changed from a logic logic 1. A modem Status Interrupt will be generated. Rev. 04 — 19 June 2003 SC16C654/654D …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C654/654D provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. ...
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... EFR[5] Special Character Detect. Logic 0 = Special character detect disabled (normal default condition). Logic 1 = Special character detect enabled. The SC16C654/654D compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software fl ...
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... Philips Semiconductors 7.11 SC16C654/654D external reset conditions Table 24: Register IER ISR LCR MCR LSR MSR FCR EFR Table 25: Output TXA, TXB, TXC, TXD RTSA, RTSB, RTSC, RTSD DTRA, DTRB, DTRC, DTRD RXRDY TXRDY 8. Limiting values Table 26: In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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Table 27: DC electrical characteristics + 2 5.0 V 10%, unless otherwise specified. amb CC Symbol ...
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... Rev. 04 — 19 June 2003 SC16C654/654D 3.3 V 5.0 V Unit Min Max Min Max MHz ...
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... Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder …continued Conditions 2.5 V Min Max [ 200 - 30h t 30w t 30d t 31h Rev. 04 — 19 June 2003 SC16C654/654D 3.3 V 5.0 V Min Max Min Max ...
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... Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder t t 30w 30h t 32h t 33h t 33s t 6h VALID t 13h ACTIVE t 15d t 13w ACTIVE t 16h t 16s DATA Rev. 04 — 19 June 2003 SC16C654/654D t 32d 002aaa171 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 002aaa211 ...
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... Fig 12. General read timing in 16 mode. 9397 750 11617 Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder t 6h VALID t 7h ACTIVE ACTIVE t 12h t 12d DATA Rev. 04 — 19 June 2003 SC16C654/654D 002aaa172 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE t ACTIVE Rev. 04 — 19 June 2003 SC16C654/654D CHANGE OF STATE t 18d ACTIVE ACTIVE 19d ACTIVE ACTIVE t 18d CHANGE OF STATE © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 002aaa352 002aaa112 ...
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... Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 04 — 19 June 2003 SC16C654/654D NEXT DATA PARITY STOP START BIT BIT BIT 20d ACTIVE ...
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... Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder DATA BITS (5– DATA BITS (5– Rev. 04 — 19 June 2003 SC16C654/654D NEXT DATA PARITY STOP START BIT BIT BIT 25d ACTIVE DATA READY t ...
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... DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 04 — 19 June 2003 SC16C654/654D NEXT DATA PARITY STOP START BIT BIT BIT 24d ACTIVE 002aaa116 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Philips Semiconductors Fig 19. Transmit ready timing in non-FIFO mode. 9397 750 11617 Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder Rev. 04 — 19 June 2003 SC16C654/654D © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 04 — 19 June 2003 SC16C654/654D PARITY STOP BIT BIT D6 D7 002aaa346 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder UART FRAME DATA TX BIT TIME RX BIT TIME DATA Rev. 04 — 19 June 2003 SC16C654/654D DATA BITS 1/2 BIT TIME 3/16 BIT TIME 002aaa212 0-1 16X CLOCK DELAY ...
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... 24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07 0.958 0.958 0.93 0.93 0.995 0.995 0.048 0.05 0.950 0.950 0.89 0.89 0.985 0.985 0.042 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 04 — 19 June 2003 SC16C654/654D SOT188 detail X (1) ( max. max. 1.44 0.18 0.18 0.1 2.16 2.16 1.02 45 ...
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... 2 scale (1) ( 0.18 10.1 10.1 12.15 12.15 0.5 1 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 19 June 2003 SC16C654/654D SOT314 detail X (1) ( 0.75 1.45 1.45 7 0.2 0.12 0.1 o 0.45 1.05 1.05 0 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-25 © ...
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... Product data Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder 2.5 mm thick/large packages. Rev. 04 — 19 June 2003 SC16C654/654D 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , [5] , SO, SOJ Rev. 04 — 19 June 2003 SC16C654/654D Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable ...
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... I characteristics”: add Table note Rev. 04 — 19 June 2003 SC16C654/654D 10 C measured in the atmosphere of the reflow : change all values nom. CCsleep 2, its reference to parameter ‘IOW © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Rev. 04 — 19 June 2003 SC16C654/654D Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC16C654/654D external reset conditions © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...