sc16c654 NXP Semiconductors, sc16c654 Datasheet - Page 23

• Manufacturer Part Number: sc16c654
• Description: Quad Uart With 64-byte Fifo And Infrared Irda Encoder/decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 11617
Product data
7.3.1 DMA mode
7.3.2 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive
FIFO trigger levels, and select the DMA mode.
Mode 0 (FCR bit 3 = 0):
receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = 1):
transmit interrupt is set when the transmit FIFO is below the programmed trigger
level. TXRDY remains a logic 0 as long as one empty FIFO location is available. The
receive interrupt is set when the receive FIFO fills to the programmed trigger level.
However, the FIFO continues to fill regardless of the programmed level until the FIFO
is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the
programmed trigger level.
Table 10:
Bit
7-6
5-4
3
Symbol
FCR[7]
(MSB),
FCR[6]
(LSB)
FCR[5]
(MSB),
FCR[4]
(LSB)
FCR[3]
FIFO Control Register bits description
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 04 — 19 June 2003
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to
TX trigger.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C654/654D will issue a transmit empty interrupt
when the number of characters in FIFO drops below the selected trigger
level. Refer to
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C654/654D is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C654/654D is in
mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;
FCR[3] = logic 0) and there is at least one character in the receive FIFO,
the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a
logic 1 when there are no more characters in the receiver.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Set and enable the interrupt for each single transmit or
Set and enable the interrupt in a block mode operation. The
Table
12.
Table
SC16C654/654D
11.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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