sc16c654 NXP Semiconductors, sc16c654 Datasheet - Page 11

• Manufacturer Part Number: sc16c654
• Description: Quad Uart With 64-byte Fifo And Infrared Irda Encoder/decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6. Functional description
9397 750 11617
Product data
The SC16C654/654D provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character. Data integrity is insured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex,
especially when manufactured on a single integrated silicon chip. The
SC16C654/654D represents such an integration with greatly enhanced features. The
SC16C654/654D is fabricated with an advanced CMOS process to achieve low drain
power and high speed requirements.
The SC16C654/654D is an upward solution that provides 64 bytes of transmit and
receive FIFO memory, instead of 16 bytes provided in the 16C554, or none in the
16C454. The SC16C654/654D is designed to work with high speed modems and
shared network environments that require fast data processing time. Increased
performance is realized in the SC16C654/654D by the larger transmit and receive
FIFOs. This allows the external processor to handle more networking tasks within a
given time. For example, the SC16C554 with a 16-byte FIFO unloads 16 bytes of
receive data in 1.53 ms. (This example uses a character length of 11 bits, including
start/stop bits at 115.2 kbit/s.) This means the external CPU will have to service the
receive FIFO at 1.53 ms intervals. However, with the 64-byte FIFO in the
SC16C654/654D, the data buffer will not require unloading/loading for 6.1 ms. This
increases the service interval, giving the external CPU additional time for other
applications and reducing the overall UART interrupt servicing time. In addition, the
four selectable levels of FIFO trigger interrupt and automatic hardware/software flow
control is uniquely provided for maximum data throughput performance, especially
when operating in a multi-channel environment. The combination of the above greatly
reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C654/654D combines the package interface modes of the 16C454/554 and
68C454/554 series on a single integrated chip. The 16 mode interface is designed to
operate with the Intel-type of microprocessor bus, while the 68 mode is intended to
operate with Motorola and other popular microprocessors. Following a reset, the
SC16C654/654D is downward compatible with the 16C454/554 or the 68C454/554,
dependent on the state of the interface mode selection pin, 16/68.
The SC16C654/654D is capable of operation to 1.5 Mbits/s with a 24 MHz crystal and
up to 5 Mbits/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the max speed
is 3 Mbits/s). With a crystal of 14.7464 MHz, and through a software option, the user
can select data rates up to 460.8 kbits/s or 921.6 kbits/s, 8 times faster than the
16C554.
The rich feature set of the SC16C654/654D is available through internal registers.
Automatic hardware/software flow control, selectable transmit and receive FIFO
trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface,
modem interface controls, and a sleep mode are all standard features. MCR[5]
provides a facility for turning off (Xon) software flow control with any incoming (RX)
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 04 — 19 June 2003
SC16C654/654D
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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