sc16c654 NXP Semiconductors, sc16c654 Datasheet - Page 25

• Manufacturer Part Number: sc16c654
• Description: Quad Uart With 64-byte Fifo And Infrared Irda Encoder/decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 11617
Product data
7.4 Interrupt Status Register (ISR)
The SC16C654/654D provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 13:
Table 14:
Priority
level
1
2
2
3
4
5
6
Bit
7-6
5-4
3-1
0
ISR[5]
0
0
0
0
0
0
1
Interrupt source
Interrupt Status Register bits description
Symbol
ISR[7-6]
ISR[5-4]
ISR[3-1]
ISR[0]
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
ISR[4]
0
0
0
0
0
1
0
Rev. 04 — 19 June 2003
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
ISR[3]
0
0
1
0
0
0
0
Table 13 “Interrupt source”
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
SC16C654/654D
ISR[0]
0
0
0
0
0
0
0
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY (Transmitter
Holding Register Empty)
MSR (Modem Status
Register)
RXRDY (Received Xoff
signal) / Special character
CTS, RTS change of state
shows the data values
Table
13).
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