SCC2698BC1A84,512 NXP Semiconductors, SCC2698BC1A84,512 Datasheet - Page 8
![IC UART OCTAL ENHANCED 84-PLCC](/photos/6/98/69866/568-84-plcc_sot189-2_sml.jpg)
SCC2698BC1A84,512
Manufacturer Part Number
SCC2698BC1A84,512
Description
IC UART OCTAL ENHANCED 84-PLCC
Manufacturer
NXP Semiconductors
Type
Octal UARTr
Datasheet
1.SCC2698BC1A84512.pdf
(29 pages)
Specifications of SCC2698BC1A84,512
Number Of Channels
8
Package / Case
84-LCC (J-Lead)
Features
False-start Bit Detection
Fifo's
3Bit
Voltage - Supply
5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
115.2 Kbps
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Supply Current
30 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Transmitter And Receiver Fifo Counter
No
Operating Supply Voltage (typ)
5V
Package Type
PLCC
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Mounting
Surface Mount
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1120-5
933976250512
SCC2698BC1A84
933976250512
SCC2698BC1A84
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SCC2698BC1A84,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
periods. These clocks may be used by any or all of the receivers
and transmitters in the OCTART or may be directed to an I/O pin for
miscellaneous use.
Counter/Timer programming
The counter timer is a 16–bit programmable divider that operates in
one of three modes: counter, timer, and time out.
The C/T uses the numbers loaded into the Counter/Timer Lower
Register (CTPL) and the Counter/Timer Upper Register (CTPU) as
its divisor. The counter timer is controlled with six commands:
Start/Stop C/T, Read/Write Counter/Timer lower register and
Read/Write Counter/Timer upper register. These commands have
slight differences depending on the mode of operation. Please see
the detail of the commands under the CTPL/CTPU register
descriptions.
Baud Rate Generation
When these timers are selected as baud rates for receiver or trans-
mitter via the Clock Select register their output will be configured as
a 16x clock. Therefore one needs to program the timers to generate
a clock 16 times faster than the data rate. The formula for calculat-
ing ’n’, the number loaded to the CTPU and CTPL registers, based
on a particular input clock frequency is shown below.
For the timer mode the formula is as follows:
NOTE: ‘n’ may not assume values of 0 and 1.
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and receiv-
er state machines include divide by 16 circuits, which provide the
final frequency and provide various timing edges used in the qualify-
ing the serial data bit stream. Often this division will result in a non–
integer value: 26.3 for example. One may only program integer
numbers to a digital divider. There for 26 would be chosen. If 26.7
were the result of the division then 27 would be chosen. This gives
a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage
error of 1.14% or 1.12% respectively, well within the ability of the
asynchronous mode of operation. Higher input frequency to the
counter reduces the error effect of the fractional division
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is com-
municating may also have a small error in the precise baud rate. In
a ”clean” communications environment using one start bit, eight data
bits and one stop bit the total difference allowed between the trans-
mitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
Receiver and Transmitter
The Octal UART has eight full-duplex asynchronous
receiver/transmitters. The operating frequency for the receiver and
transmitter can be selected independently from the baud rate
generator, the counter/timer, or from an external input.
Registers associated with the communications channel are the
mode registers (MR1 and MR2), the clock select register (CSR), the
command register (CR), the status register (SR), the transmit
holding register (THR), and the receive holding register (RHR).
2006 Aug 07
n=
Timer mode generates a square wave.
Counter mode generates a time delay.
Time out mode counts time between received characters.
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2
Clockinputfrequency
16
Baudratedesired
8
transmit FIFO, or 2) the transmitter is disabled and then re–enabled.
Transmitter
The SCC2698 is conditioned to transmit data when the transmitter is
enabled through the command register. The SCC2698 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to gen-
erate an interrupt request at MPO or MPP1 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMT bits will be set
in the status register. When a character is loaded to the transmit
FIFO the TxEMT bit will be reset. The TxEMT will not set until: 1)
the transmit FIFO is empty and the transmit shift register has fin-
ished transmitting the stop bit of the last character written to the
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled, it continues operating until the charac-
ter currently being transmitted and any characters in the TxFIFO
including parity and stop bit(s) have been completed.
The transmitter can be forced to send a continuous Low condition by
issuing a send break command from the command register. The
transmitter output is returned to the normal high with a stop break
command.
The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation.
If CTS option is enabled (MR2[4] = 1), the CTSN input at MPI0 must
be Low in order for the character to be transmitted. The transmitter
will check the state of the CTS input at the beginning of each char-
acter transmitted. If it is found to be High, the transmitter will delay
the transmission of any following characters until the CTS has re-
turned to the low state. CTS going high during the serialization of a
character will not affect that character.
Transmitter “RS485 turnaround”
The transmitter can also control the RTSN outputs, MPO via
MR2[5]. When this mode of operation is set, the meaning of the
MPO signal will usually be ‘end of message’. See description of the
MR2[5] bit for more detail.
Transmitter Flow control
The transmitter may be controlled by the CTSN input when enabled
by MR2(4). The CTSN input would be connected to RTSN output of
the receiver to which it is communicating. See further description in
the MR 1 and MR2 register descriptions.
Receiver
The SCC2698 is conditioned to receive data when enabled through
the command register. The receiver looks for a High–to–Low
(mark–to–space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16X
clock for 7–1/2 clocks (16X clock mode) or at the next rising edge of
SCC2698B
Product data sheet