SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 27

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
SC16IS741_1
Product data sheet
8.10 Enhanced Features Register (EFR)
8.11 Division registers (DLL, DLH)
This 8-bit register enables or disables the enhanced features of the UART.
shows the enhanced feature register bit settings.
Table 22.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Remark: DLL and DLH can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
Bit
7
6
5
4
3:0
Symbol
EFR[7]
EFR[6]
EFR[5]
EFR[4]
EFR[3:0]
Enhanced Features Register bits description
Combinations of software flow control can be selected by programming these
Description
CTS flow control enable
RTS flow control enable.
Special character detect
Enhanced functions enable bit
bits. See
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the
receiver FIFO resume transmission trigger level TCR[7:4] is reached.
logic 0 = Special character detect disabled (normal default condition)
logic 1 = Special character detect enabled. Received data is compared with
Xoff2 data. If a match occurs, the received data is transferred to FIFO and
IIR[4] is set to a logical 1 to indicate a special character has been detected.
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] so
that they can be modified.
Single UART with I
Rev. 01 — 29 April 2010
Table 3 “Software flow control options
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
(EFR[3:0])”.
SC16IS741
© NXP B.V. 2010. All rights reserved.
Table 22
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