SC16C850IET,157 NXP Semiconductors, SC16C850IET,157 Datasheet - Page 16
![IC UART SINGLE W/FIFO 36-TFBGA](/photos/6/98/69857/36-tfbga_sot912-1_pkg_sml.jpg)
SC16C850IET,157
Manufacturer Part Number
SC16C850IET,157
Description
IC UART SINGLE W/FIFO 36-TFBGA
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C850IBS128.pdf
(55 pages)
Specifications of SC16C850IET,157
Features
Programmable
Number Of Channels
1, UART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
2.5 V ~ 3.3 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
36-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935284685157
SC16C850IET
SC16C850IET
SC16C850IET
SC16C850IET
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C850IET,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC16C850
Product data sheet
6.10 Loopback mode
Table 7.
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see
In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins, and instead are connected together
internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control
input pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2]
(OP1). Loopback test data is entered into the transmit holding register via the user data
bus interface, D[7:0]. The transmit UART serializes the data and passes the serial data to
the receive UART via the internal loopback connection. The receive UART converts the
serial data back into parallel data that is then made available at the user data interface
D[7:0]. The user optionally compares the received data to the initial transmitted data for
verifying error-free operation of the UART TX/RX circuits.
In this mode, the interrupt pin is 3-stated, therefore, the software must use the polling
method (see
Output
baud rate
(bit/s)
38.4 k
57.6 k
115.2 k
Figure
Baud rate generator programming table using a 1.8432 MHz clock when
MCR[7] = 0 and CLKPRES[3:0] = 0
9). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
Section
1
Output
16× clock divisor
(decimal)
3
2
All information provided in this document is subject to legal disclaimers.
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.2.2) to send and receive data.
Rev. 2 — 11 November 2010
01
Output
16× clock divisor
(hexadecimal)
03
02
…continued
DLM
program value
(hexadecimal)
00
00
00
SC16C850
© NXP B.V. 2010. All rights reserved.
DLL
program value
(hexadecimal)
03
02
01
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