SC16IS752IPW,128 NXP Semiconductors, SC16IS752IPW,128 Datasheet - Page 27

• Manufacturer Part Number: SC16IS752IPW,128
• Description: IC DUAL UART 64BYTE 28TSSOP
• Manufacturer: NXP Semiconductors

Specifications of SC16IS752IPW,128

• Features: Low Current
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279292128; SC16IS752IPW-F; SC16IS752IPW-F

NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
8.8 Line Status Register (LSR)
Table 20
Table 20.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
Bit
7
6
5
4
3
2
1
0
shows the Line Status Register bit settings.
Symbol
LSR[7]
LSR[6]
LSR[5]
LSR[4]
LSR[3]
LSR[2]
LSR[1]
LSR[0]
Line Status Register bits description
Dual UART with I
Description
FIFO data error.
THR and TSR empty. This bit is the Transmit Empty indicator.
THR empty. This bit is the Transmit Holding Register Empty indicator.
Break interrupt.
Framing error.
Parity error.
Overrun error.
Data in receiver.
Rev. 07 — 19 May 2008
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error, or break indication is in
the receiver FIFO. This bit is cleared when no more errors are present
in the FIFO.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
logic 0 = Transmit Hold Register is not empty.
logic 1 = Transmit Hold Register is empty. The host can now load up to
64 characters of data into the THR if the TX FIFO is enabled.
logic 0 = no break condition (normal default condition).
logic 1 = a break condition occurred and associated character is 0x00
(RX was LOW for one character time frame)
logic 0 = no framing error in data being read from RX FIFO (normal
default condition)
logic 1 = framing error occurred in data being read from RX FIFO
(received data did not have a valid stop bit)
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
© NXP B.V. 2008. All rights reserved.
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