SC16C2550BIBS,157 NXP Semiconductors, SC16C2550BIBS,157 Datasheet - Page 16

• Manufacturer Part Number: SC16C2550BIBS,157
• Description: IC DUART SOT617-1
• Manufacturer: NXP Semiconductors

Specifications of SC16C2550BIBS,157

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 3.5 V ~ 4.5 V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280309157; SC16C2550BIBS; SC16C2550BIBS

NXP Semiconductors
SC16C2550B_5
Product data sheet
7.2 Interrupt Enable Register (IER)
prevent false starts. On the falling edge of a start or false start bit, an internal receiver
counter starts counting clocks at the 16 clock rate. After 7
should be shifted to the center of the start bit. At this time the start bit is sampled and if it
is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver
from assembling a false character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 9.
Bit
7:4
3
2
1
0
Symbol
IER[7:4]
IER[3]
IER[2]
IER[1]
IER[0]
Interrupt Enable Register bits description
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Description
not used
Modem Status Interrupt. This interrupt will be issued whenever there is a
modem status change as reflected in MSR[3:0].
Receive Line Status interrupt. This interrupt will be issued whenever a
receive data error condition exists as reflected in LSR[4:1].
Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will
be issued whenever the THR is empty and is associated with LSR[5]. In the
FIFO modes, this interrupt will be issued whenever the FIFO is empty.
Receive Holding Register. In the 16C450 mode, this interrupt will be issued
when the RHR has data or is cleared when the RHR is empty. In the FIFO
mode, this interrupt will be issued when the FIFO has reached the
programmed trigger level or is cleared when the FIFO drops below the
trigger level.
logic 0 = disable the Modem Status Register interrupt (normal default
condition)
logic 1 = enable the Modem Status Register interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt
logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal
default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
Rev. 05 — 12 January 2009
1
2
SC16C2550B
clocks, the start bit time
© NXP B.V. 2009. All rights reserved.
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