sc16c2550b NXP Semiconductors, sc16c2550b Datasheet
sc16c2550b
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sc16c2550b Summary of contents
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... An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2550B operates 3.3 V and 2.5 V and the industrial temperature range, and is available in plastic PLCC44, LQFP48, DIP40 and HVQFN32 packages. 2. Features ...
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... DIP40 3.1 Ordering options Table 2. Type number SC16C2550BIA44 SC16C2550BIBS SC16C2550BIB48 SC16C2550BIN40 SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Description plastic leaded chip carrier; 44 leads plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 mm plastic low profi ...
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... RESET REGISTER CSA SELECT CSB INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC16C2550B SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs AND LOGIC LOGIC CLOCK AND BAUD RATE GENERATOR LOGIC XTAL1 Rev. 04 — ...
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... RXB 9 RXA 10 TXA 11 12 TXB OP2B 13 CSA 14 15 CSB XTAL1 16 XTAL2 17 IOW 18 19 CDB GND 20 002aaa596 Rev. 04 — 15 February 2007 SC16C2550B 24 RESET 23 RTSA 22 OP2A 21 INTA 20 INTB 002aab746 RIA 38 CDA 37 DSRA 36 CTSA 35 RESET 34 DTRB ...
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... TXB 14 OP2B 15 CSA 16 17 CSB RXB RXA 5 TXRDYB 6 SC16C2550BIB48 TXA 7 8 TXB OP2B 9 CSA 10 11 CSB 12 n.c. Rev. 04 — 15 February 2007 SC16C2550B 39 RESET 38 DTRB 37 DTRA 36 RTSA 35 OP2A 34 RXRDYA 33 INTA 32 INTB 002aaa597 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A ...
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... I Read strobe (active LOW strobe). A logic 0 transition on this pin will load the contents of an internal register defined by address bits onto the SC16C2550B data bus (D0 to D7) for access by external CPU Write strobe (active LOW strobe). A logic 0 transition on this pin will transfer the contents of the data bus (D0 to D7) from the external CPU to an internal register that is defi ...
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... UART channels, A through B. A logic 0 on the CTS 23 I pin indicates the modem or data set is ready to accept transmit data from the SC16C2550B. Status can be tested by reading MSR[4]. This pin has no effect on the UART’s transmit or receive operation. Rev. 04 — 15 February 2007 ...
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... UART channels, A through logic 0 on this pin indicates that the SC16C2550B is powered-on and ready. This pin can be controlled via the Modem Control Register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0] or after a reset. This pin has no effect on the UART’ ...
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... The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance and reduces power consumption. The SC16C2550B is capable of operation Mbit/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460 ...
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... CSA, CSB = 1 CSA = 0 CSB = 0 6.2 Internal registers The SC16C2550B provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control ...
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... Hardware/software and time-out interrupts The interrupts are enabled by IER[3:0]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit the SC16C2550B will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR register provides the current singular highest priority interrupt only ...
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... TX/RX channel control. The programmable baud rate generator is capable of operating with a frequency MHz. To obtain maximum data rate necessary to use full rail swing on the clock input. The SC16C2550B can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins ...
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... FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC16C2550B sets the TXRDY (or RXRDY) output pin when characters in the transmit FIFO is below 16 or the characters in the receive FIFOs are above the receive trigger level ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs TRANSMIT FIFO REGISTERS RECEIVE FIFO REGISTERS CLOCK AND BAUD RATE GENERATOR XTAL2 XTAL1 Rev. 04 — 15 February 2007 SC16C2550B TRANSMIT TXA, TXB SHIFT REGISTER MCR[ RECEIVE SHIFT RXA, RXB REGISTER RTSA, RTSB CTSA, CTSB DTRA, DTRB ...
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... FIFO/THR, logic 1 = FIFO/THR empty). The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550B and receive FIFO by reading the RHR register. The receive section provides a mechanism to ...
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... FIFO drops below the trigger level. logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition) logic 1 = enable the RXRDY (ISR level 2) interrupt Rev. 04 — 15 February 2007 SC16C2550B 1 clocks, the start bit time 2 © NXP B.V. 2007. All rights reserved ...
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... ISR register or by loading the THR with new data characters. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2550B in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status ...
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... LQFP48 packages will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode ‘1’: When the SC16C2550B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached or a Receive Time-out has occurred, the RXRDY pin on PLCC44 and LQFP48 packages will logic 0 ...
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... Interrupt Status Register (ISR) The SC16C2550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced ...
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... Description ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being used in the 16C450 mode. They are set to a logic 1 when the FIFOs are enabled in the SC16C2550B mode. logic 0 or cleared = default condition ISR[5:4] not used ISR[3:1] INT priority bits 2:0 ...
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... INT (A, B outputs to the active mode and sets OP2 to a logic 0 MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC16C2550B. This bit is instead used in the Loop-back mode only. In the Loop-back mode, this bit is used to write the state of the modem RI interface signal. MCR[1] ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2550B and the CPU. Table 19. Bit SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Line Status Register bits description ...
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... A modem Status Interrupt will be generated. [1] MSR[2] RI logic change (normal default condition) logic 1 = the RI input to the SC16C2550B has changed from a logic logic 1. A modem Status Interrupt will be generated. [1] MSR[1] DSR logic DSR change (normal default condition) logic 1 = the DSR input to the SC16C2550B has changed state since the last time it was read ...
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... NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC16C2550B provides a temporary data register to store 8 bits of user information. 7.10 SC16C2550B external reset condition Table 21. Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 22. Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB ...
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... (other outputs (data bus (other outputs 800 A 1.85 OH (data bus 400 A 1.85 OH (other outputs MHz - - Rev. 04 — 15 February 2007 SC16C2550B Min Max - 7 GND 0 0 +85 65 +150 - 500 Max Min Max Min 0.45 0.3 0.6 0 ...
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... T RCLK 25 pF load - 100 - 100 [3] 8T 24T RCLK - 100 [ RCLK - 100 - 100 Rev. 04 — 15 February 2007 SC16C2550B Min Max Min - ...
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... CC Conditions Min [3] - 200 valid address t 13h active t t 13d 15d t 13w active t 16h t 16s data Rev. 04 — 15 February 2007 SC16C2550B Max Min Max Min RCLK RCLK - 5.0 V Unit CC Max ...
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... Rev. 04 — 15 February 2007 SC16C2550B 002aaa110 change of state t 18d active active t 19d active active t 18d change of state 002aaa352 © NXP B.V. 2007. All rights reserved ...
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... data bits 6 data bits 7 data bits 16 baud rate clock Rev. 04 — 15 February 2007 SC16C2550B next data parity stop start bit bit bit 20d active t 21d active 002aaa113 © NXP B.V. 2007. All rights reserved. ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit data bits ( start bit data bits ( Rev. 04 — 15 February 2007 SC16C2550B next data parity stop start bit bit bit 25d active data ready t 26d ...
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... 27d active transmitter ready Rev. 04 — 15 February 2007 SC16C2550B next data parity stop start bit bit bit 24d active 002aaa116 next data parity stop ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit data bits ( data bits 6 data bits 7 data bits t 28d t 27d FIFO full Rev. 04 — 15 February 2007 SC16C2550B parity stop bit bit 002aaa581 © NXP B.V. 2007. All rights reserved ...
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... 0.81 16.66 16.66 16.00 16.00 17.65 1.27 0.66 16.51 16.51 14.99 14.99 17.40 0.032 0.656 0.656 0.63 0.63 0.695 0.05 0.026 0.650 0.650 0.59 0.59 0.685 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 04 — 15 February 2007 SC16C2550B detail 17.65 1.22 1.44 0.18 0.18 0.1 17.40 1.07 1.02 0.695 0.048 0.057 0.007 0.007 0.004 ...
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... 2.5 scale (1) ( 5.1 3.25 5.1 3.25 0.5 3.5 4.9 2.95 4.9 2.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 04 — 15 February 2007 SC16C2550B detail 0.5 0.05 0.1 3.5 0.1 0.05 0.3 EUROPEAN PROJECTION SOT617 ISSUE DATE 01-08-08 02-10-18 © NXP B.V. 2007. All rights reserved. ...
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... 2.5 scale (1) ( 0.27 0.18 7.1 7.1 9.15 9.15 0.5 0.17 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 15 February 2007 SC16C2550B detail 0.75 0.95 1 0.2 0.12 0.1 0.45 0.55 EUROPEAN PROJECTION SOT313 ( ...
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... scale (1) ( 1.70 0.53 0.36 52.5 14.1 1.14 0.38 0.23 51.5 13.7 0.067 0.021 0.014 2.067 0.56 0.045 0.015 0.009 2.028 0.54 REFERENCES JEDEC JEITA MO-015 SC-511-40 Rev. 04 — 15 February 2007 SC16C2550B 3.60 15.80 17.42 2.54 15.24 3.05 15.24 15.90 0.14 0.62 0.69 0.1 0.6 0.12 0.60 0.63 EUROPEAN PROJECTION SOT129 ...
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... Table 26 SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 27 Rev. 04 — 15 February 2007 SC16C2550B stg(max) Figure 22) than a PbSn process, thus © NXP B.V. 2007. All rights reserved the ...
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... Volume (mm < 350 260 260 250 Figure 22. maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level Rev. 04 — 15 February 2007 SC16C2550B 3 ) 350 220 220 3 ) 350 to 2000 > 2000 260 260 250 245 245 ...
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... Through-hole-surface PMFP mount SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs [1] Soldering method Wave suitable suitable not suitable Rev. 04 — 15 February 2007 SC16C2550B [2] Reflow [3] not suitable Dipping suitable © NXP B.V. 2007. All rights reserved ...
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... Wave [5] , LBGA, not suitable [5] , TFBGA, not suitable , SO, SOJ suitable not recommended not recommended [10] [10] , WQCCN..L not suitable Rev. 04 — 15 February 2007 SC16C2550B …continued [2] Reflow suitable [6] suitable suitable [7][8] suitable [9] suitable not suitable © NXP B.V. 2007. All rights reserved. Dipping ...
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... Data sheet status Product data sheet “Features”: added (new) third bullet item Section 3.1 “Ordering options” Product data sheet Product data Product data Rev. 04 — 15 February 2007 SC16C2550B Change notice Supersedes - SC16C2550B_3 - SC16C2550B-02 - SC16C2550B- © NXP B.V. 2007. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 04 — 15 February 2007 SC16C2550B © NXP B.V. 2007. All rights reserved ...
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... Interrupt Status Register (ISR 7.5 Line Control Register (LCR 7.6 Modem Control Register (MCR 7.7 Line Status Register (LSR 7.8 Modem Status Register (MSR 7.9 Scratchpad Register (SPR 7.10 SC16C2550B external reset condition . . . . . . 24 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 26 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 27 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 12 Soldering ...