SC16C2552BIA44,512 NXP Semiconductors, SC16C2552BIA44,512 Datasheet - Page 14

• Manufacturer Part Number: SC16C2552BIA44,512
• Description: IC UART DUAL SOT187-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C2552BIA44,512

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274408512; SC16C2552BIA44; SC16C2552BIA44

NXP Semiconductors
SC16C2552B_3
Product data sheet
7.3.1.1 Mode 0 (FCR bit 3 = 0)
7.3.1.2 Mode 1 (FCR bit 3 = 1)
7.3.1 DMA mode
7.3.2 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels and select the DMA mode.
Set and enable the interrupt for each single transmit or receive operation and is similar to
the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) at the MFn pin will go to a logic 0 whenever the Receive Holding Register (RHR)
is loaded with a character and AFR[2:1] is set to the RXRDY mode.
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO has at least one empty location. TXRDY remains a logic 0 as long as
one empty FIFO location is available. The receive interrupt is set when the receive FIFO
fills to the programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDY at the MFn pin remains a logic 0 as long
as the FIFO fill level is above the programmed trigger level, and AFR[2:1] is set to the
RXRDY mode.
Table 8.
Bit
7:6
5:4
3
FIFO Control Register bits description
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 03 — 12 February 2009
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to
Not used; initialized to logic 0.
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C2552B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there
are no characters in the transmit FIFO or Transmit Holding Register, the
TXRDYn pin will be a logic 0. Once active, the TXRDYn pin will go to a
logic 1 after the first character is loaded into the Transmit Holding
Register.
Receive operation in mode ‘0’: When the SC16C2552B is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY signal at
the MFn pin will be a logic 0. Once active, the RXRDY signal at the
MFn pin will go to a logic 1 when there are no more characters in the
receiver. Note that the AFR register must be set to the RXRDY mode
prior to any possible reading of the RXRDY signal.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Table
9.
SC16C2552B
© NXP B.V. 2009. All rights reserved.
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