SC16C2552BIA44,512 NXP Semiconductors, SC16C2552BIA44,512 Datasheet - Page 15

• Manufacturer Part Number: SC16C2552BIA44,512
• Description: IC UART DUAL SOT187-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C2552BIA44,512

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274408512; SC16C2552BIA44; SC16C2552BIA44

NXP Semiconductors
SC16C2552B_3
Product data sheet
Table 8.
Table 9.
Bit
3
(continued)
2
1
0
FCR[7]
0
0
1
1
FIFO Control Register bits description
RCVR trigger levels
Symbol
FCR[2]
FCR[1]
FCR[0]
FCR[6]
0
1
0
1
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 03 — 12 February 2009
Description
Transmit operation in mode ‘1’: When the SC16C2552B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 if
one or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C2552B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-out has occurred, the RXRDY signal at the
MFn pin will go to a logic 0. Once activated, it will go to a logic 1 after
there are no more characters in the FIFO. Note that the AFR register
must be set to the RXRDY mode prior to any possible reading of the
RXRDY signal.
XMIT FIFO reset.
RCVR FIFO reset.
FIFOs enabled.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the Transmit Shift Register is not cleared or altered).
This bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the Receive Shift Register is not cleared or altered).
This bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to or they will not be
programmed.
RX FIFO trigger level
01
04
08
14
…continued
SC16C2552B
© NXP B.V. 2009. All rights reserved.
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