SC16C654DBIB64,128 NXP Semiconductors, SC16C654DBIB64,128 Datasheet - Page 28
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SC16C654DBIB64,128
Manufacturer Part Number
SC16C654DBIB64,128
Description
IC QUAD UART 64BYTE 64LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C654BIBS528.pdf
(58 pages)
Specifications of SC16C654DBIB64,128
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935276671128
SC16C654DBIB64-F
SC16C654DBIB64-F
SC16C654DBIB64-F
SC16C654DBIB64-F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654DBIB64,128
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 14965
Product data sheet
Table 10:
Table 11:
Table 12:
Bit
3
(cont.)
2
1
0
FCR[7]
0
0
1
1
FCR[5]
0
0
1
1
Symbol
FCR[3]
(continued)
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
RX trigger levels
TX trigger levels
FCR[6]
0
1
0
1
FCR[4]
0
1
0
1
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 02 — 20 June 2005
Description
Transmit operation in mode ‘1’: When the SC16C654B/654DB is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 when
the trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C654B/654DB is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has
been reached, or a Receive Time-Out has occurred, the RXRDY pin will
go to a logic 0. Once activated, it will go to a logic 1 after there are no
more characters in the FIFO.
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to, or they will not be
programmed.
RX FIFO trigger level
08
16
56
60
TX FIFO trigger level (# of characters)
08
16
32
56
…continued
SC16C654B/654DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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