SC28C94A1A,512 NXP Semiconductors, SC28C94A1A,512 Datasheet - Page 6

• Manufacturer Part Number: SC28C94A1A,512
• Description: IC UART QUAD W/FIFO 52-PLCC
• Manufacturer: NXP Semiconductors
• Type: Quad UARTr

Specifications of SC28C94A1A,512

• Number Of Channels: 4, QUART
• Package / Case: 52-PLCC
• Features: False-start Bit Detection
• Fifo's: 8 Byte
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current: 35 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3993-5; 935262534512; SC28C94A1A; SC28C94A1A

Philips Semiconductors
Table 1.
NOTES:
1. Registers not explicitly reset by hardware reset power up randomly.
2. In X1/CLK divide by 2 all circuits receive the divided clock except the BRG and change-of-state detectors.
2006 Aug 09
110000–111000
111010–111111
Quad universal asynchronous receiver/transmitter (QUART)
000000
000001
000010
000100
000101
001000
001001
001010
010000
010001
010010
010100
010101
100000
100001
100010
100100
100101
101000
101001
101010
000011
000110
000111
001011
001100
001101
001110
001111
010011
010110
010111
011000
011001
011010
011011
011100
011101
011110
100011
100110
100111
101011
101100
101101
101110
101111
111001
011111
A5:0
QUART Registers
Mode Register a (MR0a, MR1a, MR2a)
Status Register a (SRa)
Reserved
Receive Holding Register a (RxFIFOa)
Input Port Change Reg ab (IPCRab)
Interrupt Status Reg ab (ISRab)
Counter/Timer Upper ab (CTUab)
Counter/Timer Lower ab (CTLab)
Mode Register b (MR0b, MR1b, MR2b)
Status Register b (SRb)
Reserved
Receive Holding Register b (RxFIFOb)
Output Port Register ab (OPRab)
Input Port Register ab (IPRab)
Start Counter ab
Stop Counter ab
Mode Register c (MR0c, MR1c, MR2c)
Status Register c (SRc)
Reserved
Receive Holding Register c (RxFIFOc)
Input Port Change Reg cd (IPCRcd)
Interrupt Status Reg cd (ISRcd)
Counter/Timer Upper cd (CTUcd)
Counter/Timer Lower cd (CTLcd)
Mode Register d (MR0d, MR1d, MR2d)
Status Register d (SRd)
Reserved
Receive Holding Register d (RxFIFOd)
Output Port Register cd (OPRcd)
Input Port Register cd (IPRcd)
Start Counter cd
Stop Counter cd
Bidding Control Register a (BCRa)
Bidding Control Register b (BCRb)
Bidding Control Register c (BCRc)
Bidding Control Register d (BCRd)
Reserved
Reserved
Reserved
Reserved
Current Interrupt Register (CIR)
Global Interrupting Channel Reg (GICR)
Global Int Byte Count Reg (GIBCR)
Global Receive Holding Reg (GRxFIFO)
Interrupt Control Register (ICR)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
READ (RDN = Low)
6
Mode Register a (MR0a, MR1a, MR2a)
Clock Select Register a (CSRa)
Command Register a (CRa)
Transmit Holding Register a (TxFIFOa)
Auxiliary Control Reg ab (ACRab)
Interrupt Mask Reg ab (IMRab)
Counter/Timer Upper Reg ab (CTURab)
Counter/Timer Lower Reg ab (CTLRab)
Mode Register b (MR0b, MR1b, MR2b)
Clock Select Register b (CSRb)
Command Register b (CRb)
Transmit Holding Register b (TxFIFOb)
Output Port Register ab (OPRab)
I/OPCRa (I/O Port Control Reg a)
I/OPCRb (I/O Port Control Reg b)
Reserved
Mode Register c (MR0c, MR1c, MR2c)
Clock Select Register c (CSRc)
Command Register c (CRc)
Transmit Holding Register c (TxFIFOc)
Auxiliary Control Reg cd (ACRcd)
Interrupt Mask Reg cd (IMRcd)
Counter/Timer Upper Reg cd (CTURcd)
Counter/Timer Lower Reg cd (CTLRcd)
Mode Register d (MR0d, MR1d, MR2d)
Clock Select Register d (CSRd)
Command Register d (CRd)
Transmit Holding Register d (TxFIFOd)
Output Port Register cd (OPRcd)
I/OPCRc (I/O Port Control Reg c)
I/OPCRd (I/O Port Control Reg d)
Reserved
Bidding Control Register a (BCRa)
Bidding Control Register b (BCRb)
Bidding Control Register c (BCRc)
Bidding Control Register d (BCRd)
Power Down
Power Up
Disable DACKN
Enable DACKN
Reserved
Interrupt Vector Register (IVR)
Update CIR
Global Transmit Holding Reg (GTxFIFO)
Interrupt Control Register (ICR)
BRG Rate. 00 = low; 01 = high
Set X1/CLK divide by two
Set X1/CLK Normal
Reserved
Test Mode
Reserved
WRITE (WRN = Low)
2
2
(use when X1 is
SC28C94
Product data sheet
4 Mhz)